Report Timing Deep Read: Silicon PPA Impact

Silicon PPA and closure impact

Cell vs net delay split guides PD vs synthesis ownership.

Area drivers

• Upsize cells

• Buffer insertion

• Shield wires

Power drivers

• VT swap leakage

• Clock tree power for skew

Timing impact

• Net delay on critical routes

• SI delta delay

PD consequences

• Congestion limits sizing

• Layer promotion for nets

Verification burden

• ECO equivalence

• SI re-signoff

PPA — Report Timing Deep Read
area/power/timing/closure-time tradeoff

PPA takeaways

• ECO has PPA cost

• Signoff is multi-corner

Design option PPA snapshot

BEFORE / AFTER ECO — Report Timing Deep Read

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

Slack is a path story — read the graph, not just the number.

Concept diagram

TIMING GRAPH

FF --cell-- logic --net-- logic --cell-- FF
launch                              capture

Metric graph

SLACK TAIL

paths |    ***
      |  *******
      |*********  <- fix WNS first

Reports and artifacts

• WNS/TNS

• path slack histogram

• cell vs net %

• path group summary

Mini case study

WNS -90ps but 80% net delay on one congested route — PD route fix beat upsizing three cells.

Debug branches

• Cell-heavy -> sizing/VT

• Net-heavy -> route/layer

• Check launch/capture clocks

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Senior STA debug reads incremental delay, sense, edge, clock domain, and exception flags on the critical path — not just slack number.

Metric: incremental delay attribution accuracy, false debug rate