Report Timing Deep Read: Software / Programmer View

RTL / implementation view

RTL structure affects logic depth, fanout, and retiming opportunities.

What designers feel

• Surprise timing after RTL 'small' change

• Clock domain bugs

RTL structure impact

• Pipeline depth

• Reset and clock gating

• Boundary flop placement

Synthesis interaction

• Retiming constraints

• Don't care optimization vs STA

RTL-side mitigations

• Register boundaries

• Clean clocking

• Review SDC with RTL changes

RTL — Report Timing Deep Read
// pipeline stage added -> check new reg2reg path group WNS

Layer the driver touches

STA OWNERSHIP LAYERS — Report Timing Deep Read

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

Slack is a path story — read the graph, not just the number.

Concept diagram

TIMING GRAPH

FF --cell-- logic --net-- logic --cell-- FF
launch                              capture

Metric graph

SLACK TAIL

paths |    ***
      |  *******
      |*********  <- fix WNS first

Reports and artifacts

• WNS/TNS

• path slack histogram

• cell vs net %

• path group summary

Mini case study

WNS -90ps but 80% net delay on one congested route — PD route fix beat upsizing three cells.

Debug branches

• Cell-heavy -> sizing/VT

• Net-heavy -> route/layer

• Check launch/capture clocks

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Senior STA debug reads incremental delay, sense, edge, clock domain, and exception flags on the critical path — not just slack number.

Metric: incremental delay attribution accuracy, false debug rate