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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
    • Setup and Hold Closure Order
    • Physical vs Logical ECOs
      • Cell Swaps and Sizing
      • Buffering and Layers
      • Logical Changes
      • ECO Risk Ladder
    • Useful Skew Trade-offs
    • ECO Regression Matrix
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Physical vs Logical ECOs
  1. Topics
  2. Static Timing Analysis
  3. ECO and Closure
  4. Physical vs Logical ECOs
  5. Buffering and Layers

Part 8 · ECO and Closure · All levels

Buffering and Layers

Long wires are quadratic in length, so buffers split them; the right number balances wire savings against buffer delay, and a higher metal layer is an alternative.

On this page

    Why it matters

    The delay of a long unbuffered wire grows with the square of its length. Splitting it into k+1 segments with k buffers divides the wire part by k+1 but adds k buffer delays. There is an optimum. A higher metal layer has lower resistance and attacks the same problem from the other side.

    Worked example (illustrative)

    example.py
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    # 2000 um wire: r = 2 ohm/um, c = 0.2 fF/um. Distributed RC delay = 0.38 * R * C. Buffer delay 25 ps. Driver and load ignored.
    L, r, c, tb = 2000.0, 2.0, 0.2, 25.0
    RC = 0.38 * (r * L) * (c * L) / 1000.0           # ps (ohm * fF = fs)
    assert round(RC, 1) == 608.0
    def total(k, rc):
        return rc / (k + 1) + tb * k
    low = {k: round(total(k, RC), 1) for k in range(0, 7)}
    assert low == {0: 608.0, 1: 329.0, 2: 252.7, 3: 227.0, 4: 221.6, 5: 226.3, 6: 236.9}
    best_low = min(low, key=low.get)
    assert best_low == 4
    # the same wire on an upper layer with half the resistance
    RC_up = RC / 2
    up = {k: round(total(k, RC_up), 1) for k in range(0, 7)}
    best_up = min(up, key=up.get)
    assert up[0] == 304.0 and best_up == 3 and up[3] == 151.0
    print("PASS: lower layer best k =", best_low, "at", low[best_low], "ps; upper layer best k =", best_up, "at", up[best_up], "ps; no buffers on the upper layer:", up[0])

    Buffers

    0

    1

    2

    3

    4

    5

    Lower layer delay (ps)

    608

    329

    253

    227

    222

    226

    Upper layer delay (ps)

    304

    177

    151.3

    151.0

    161

    —

    An unbuffered 2 mm route takes 608 ps. One buffer halves the wire part and gives 329 ps; the best choice is four buffers at 221.6 ps, after which each extra buffer costs more than it saves. Moving the net to an upper layer with half the resistance already gives 304 ps with no buffers, and with three buffers 151 ps. Layer assignment is not free: upper layers are scarce, and a layer change is a reroute, so it carries the risk of changing coupling and congestion. On the upper layer three buffers wins narrowly over two (151.0 ps against 151.3 ps). Rounded values in the table are from the same formula; the model ignores driver and load for clarity.

    What the review looks for

    • Buffers are inserted with the wire's real extracted RC, not the model above; the formula only shows the trade-off.

    • Layer promotion is checked against congestion and against SI on the new route.

    • Buffer count is checked at the optimum: more buffers than needed waste area and power, and add variation.

    Common pitfall

    Adding buffers until the violation goes away without checking the optimum. Past the minimum each buffer makes the wire slower and uses power.

    Interview

    State why the wire delay is quadratic and what buffering does to it.

    Check yourself With 30 ps buffers instead of 25 ps, what is the best number of buffers on the lower layer?

    Four is still the best, narrowly: k = 4 gives 121.6 + 120 = 241.6 ps and k = 3 gives 152 + 90 = 242 ps. With much slower buffers the optimum would fall.

    Related topics

    • Cell Swaps and Sizing

    • Next: Logical Changes

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    See also

    • ECO Risk Ladder