Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
    • Setup and Hold Closure Order
    • Physical vs Logical ECOs
      • Cell Swaps and Sizing
      • Buffering and Layers
      • Logical Changes
      • ECO Risk Ladder
    • Useful Skew Trade-offs
    • ECO Regression Matrix
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
Loading lesson

‹Physical vs Logical ECOs
  1. Topics
  2. Static Timing Analysis
  3. ECO and Closure
  4. Physical vs Logical ECOs
  5. Logical Changes

Part 8 · ECO and Closure · All levels

Logical Changes

Restructuring logic can cut depth far more than sizing can, but it needs equivalence checking; arrival times decide the best structure.

On this page

    Why it matters

    When sizing and buffering are exhausted, the remaining lever is logic structure: re-associating an expression, moving a late input closer to the output, duplicating logic to cut fanout. These changes can save hundreds of picoseconds but alter the netlist, so function equivalence must be proven afterwards.

    Worked example (illustrative)

    example.py
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    import heapq
    gate = 40.0                                   # ps per 2-input gate
    arrivals = [0.0] * 7 + [100.0]                # eight inputs, the last arriving 100 ps late
    def chain(arr):
        t = arr[0]
        for a in arr[1:]:
            t = max(t, a) + gate
        return t
    def balanced(arr):                            # fixed balanced tree, inputs paired in order
        level = list(arr)
        while len(level) > 1:
            level = [max(level[i], level[i + 1]) + gate for i in range(0, len(level), 2)]
        return level[0]
    def arrival_aware(arr):                       # always combine the two earliest signals
        h = list(arr); heapq.heapify(h)
        while len(h) > 1:
            a, b = heapq.heappop(h), heapq.heappop(h)
            heapq.heappush(h, max(a, b) + gate)
        return h[0]
    res = (chain(arrivals), balanced(arrivals), arrival_aware(arrivals))
    assert res == (280.0, 220.0, 160.0)
    print("PASS: output arrival for chain, balanced and arrival-aware trees:", res)

    Structure

    Output arrival (ps)

    Chain of 7 gates

    280

    Balanced tree, late input at a leaf

    220

    Arrival-aware tree (late input joins last)

    160

    The same function (an 8-input associative operation) arrives at 280 ps as a chain, 220 ps as a balanced tree and 160 ps when the late input is combined last. The arrival-aware tree is 120 ps faster than the chain and 60 ps faster than the textbook-balanced one, because depth is measured from the latest input. Only associative and commutative functions can be re-associated freely; for anything else the change must preserve the exact function.

    What the review looks for

    • Equivalence checking before and after the change, run on the final netlist and not on a model.

    • New logic is placed and routed in the same flow as everything else; timing, SI and power are rerun.

    • Logical ECOs are limited to cones with timing evidence; changing logic for convenience reopens verification.

    Common pitfall

    Re-associating without checking arrival times. A balanced tree is optimal only if all inputs arrive together.

    Interview

    Explain why the late input should join last and why equivalence checking is mandatory.

    Check yourself If every input arrived at 0 ps, which structure would win?

    The balanced tree and the arrival-aware tree would tie at 120 ps (three levels of 40 ps); the chain would still take 280 ps.

    Related topics

    • Buffering and Layers

    • Next: ECO Risk Ladder

    Previous

    128 / 183

    Next: ECO Risk Ladder

    Up next

    Up nextECO Risk Ladder

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Cell Swaps and Sizing