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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
    • Scripted Flows and Regression
    • Debugging QoR
      • The QoR Debug Method
      • Reading Reports to Localise
      • Constraint Causes
      • RTL Structure Causes
      • Fanout, Black Boxes and Classifying Paths
    • Simulation-Synthesis Mismatch
  • Interview and Judgment11
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‹Debugging QoR
  1. Topics
  2. Logic Synthesis
  3. Flows and Debugging
  4. Debugging QoR
  5. Constraint Causes

Part 8 · Flows and Debugging · Intermediate

Constraint Causes

Missing constraints that hide paths and over-constraint that invents them.

On this page

    Missing constraints

    An unconstrained path reports a comfortable slack while failing in place and route. The tool optimised nothing because the ask said nothing.

    Suspect a missing constraint when slack is near zero yet the path was never a target. Check clocks, input and output delays, and false paths first.

    Missing piece

    Symptom

    Check

    Clock

    Whole domain looks untimed

    Every endpoint in the domain lacks a clock ask.

    Input or output delay

    Boundary paths pass too easily

    Port delays exist for each interface group.

    False or multicycle intent

    An impossible path dominates the worst list

    The exception is written down and reviewed, not assumed.

    Over-constraint

    An impossible ask spreads damage beyond its own path. The tool duplicates logic and grows area along many paths to chase one unclosable number.

    EXAMPLE parameters make the arithmetic plain. A path arrives at 4.9 ns against a 4.0 ns ask, then the ask relaxes to 5.0 ns.

    Diagram
    EXAMPLE parameters: arrival time 4.9 ns
    ask 4.0 ns: slack = 4.0 - 4.9 = -0.9 ns (misses)
    ask 5.0 ns: slack = 5.0 - 4.9 = +0.1 ns (closes)
    lesson: the same logic passes or fails on the ask alone

    Shallow logic with a large violation points at the ask. Deep logic with a proportional violation points at the structure.

    Writing the intent down

    The sketch below is illustrative SDC-style text, invented for this lesson and not tool output. Real constraint syntax and defaults vary between tools.

    Diagram
    illustrative SDC-style sketch, not a runnable script
    create_clock -period 10.0 [get_ports clk]
    set_input_delay 2.0 -clock clk [all_inputs]
    set_output_delay 2.0 -clock clk [all_outputs]
    set_false_path -from [get_ports scan_en]
    set_max_fanout 32 [current_design]

    Each line states one intent: the clock, the boundary budget, the paths to ignore, and the fanout bound. Unexplained lines do not belong in the file.

    The 32 in the sketch is this topic's EXAMPLE ask. The classifier in a later lesson treats 50 or more loads as a coarse suspect ranker, not a sign-off bound.

    Common mistakes

    Common pitfall

    Copying an exception from another block silences a real path. Every false path and multicycle needs a named reason tied to this design, reviewed before synthesis.

    Interview

    Likely probes: telling the two constraint failures apart.

    • Missing constraint: easy slack on logic that later fails downstream.

    • Over-constraint: large violation on shallow logic plus area growth nearby.

    • Both are fixed in the ask first, before any RTL edit.

    Check yourself A boundary path shows +0.1 ns slack in synthesis but fails downstream. What do you check?

    The port delays. A missing input or output delay makes synthesis grade a path the chip never sees.

    Check yourself Arrival is 4.9 ns. What slack does a 4.0 ns ask give, and what does a 5.0 ns ask give?

    -0.9 ns against 4.0 ns and +0.1 ns against 5.0 ns. The same arrival passes or fails on the ask.

    Related topics

    • Reading reports to localise

    • SDC for synthesis

    • Timing-driven synthesis

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    See also

    • The QoR Debug Method
    • Fanout, Black Boxes and Classifying Paths