Unintended latches

A combinational block that misses an assignment on some path keeps its old value. The tool builds storage, and timing through it turns murky.

The cure is structural: assign every output on every path, or move the storage into an explicit clocked block.

Deep priority logic

A nested if-else chain tests requests one at a time. The last request waits behind every earlier test, so depth grows with the request count.

The runnable Yosys block below builds an 8-request chain and pins its 7 mux stages with an assertion. The balanced depth beside it is hand arithmetic.

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read_verilog <<EOV
module prio_chain(input wire [7:0] req, output wire [2:0] idx);
assign idx = req[0] ? 3'd0 : req[1] ? 3'd1 : req[2] ? 3'd2 : req[3] ? 3'd3 : req[4] ? 3'd4 : req[5] ? 3'd5 : req[6] ? 3'd6 : 3'd7;
endmodule
EOV
hierarchy -check -top prio_chain
proc
opt_clean
select -assert-count 7 t:$mux
log PASS: 8-line priority chain holds 7 mux stages

chain stages = 8 requests - 1 = 7 mux stages (pinned by the block above)
balanced tree depth = ceil(log2(8)) = 3 stages
saved stages = 7 - 3 = 4 stages

Restructuring into a tree, a case decode, or a one-hot select removes stages. Exact gains vary between tools and libraries.

Unshared arithmetic

Two adders that never fire together still cost two adders unless the source shares them. Area reports show the same operator repeated side by side.

Sharing helps only when the operations exclude each other in time. Forcing it elsewhere adds muxing without removing area.

Common mistakes

Related topics

• Constraint causes

• Resource sharing and arithmetic inference

• Latch inference