Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
    • Scripted Flows and Regression
    • Debugging QoR
      • The QoR Debug Method
      • Reading Reports to Localise
      • Constraint Causes
      • RTL Structure Causes
      • Fanout, Black Boxes and Classifying Paths
    • Simulation-Synthesis Mismatch
  • Interview and Judgment11
Loading lesson

‹Debugging QoR
  1. Topics
  2. Logic Synthesis
  3. Flows and Debugging
  4. Debugging QoR
  5. Reading Reports to Localise

Part 8 · Flows and Debugging · Intermediate

Reading Reports to Localise

Area, fanout, and worst-path tables that point at the failing structure.

On this page

    What each report answers

    Three reports localise most QoR failures. Area by cell type names the costly structure, fanout names the heavy net, and the worst path names the failing endpoints.

    Report

    Answers

    First look

    Area by cell type

    Which logic dominates the cost

    One cell type far above its neighbours.

    Worst paths

    Which endpoints miss, and by how much

    The smallest slack and its start and end points.

    Fanout and load

    Which net drives too much

    A load far above the library guidance for its driver.

    Walking the worst path

    The table below is an illustrative layout, with numbers invented for this lesson. Real report text varies between tools, so only the invented shape is shown.

    Path

    Startpoint

    Endpoint

    Slack (ns)

    Levels

    Note

    P1

    config register

    control latch

    0.0

    2

    Just meets at 0.0 over 2 levels; suspect a missing constraint only if its endpoints lack clock, IO, or exception coverage.

    P2

    request queue

    grant output

    -1.8

    9

    Deep chain through priority logic.

    P3

    alu input A

    result register

    -0.9

    5

    Repeated arithmetic without sharing.

    Read P2 first: the largest violation with the deepest chain. Its startpoint and endpoint bound where the fix must land.

    An area recount

    Areas below are library units of the fictional teaching library course.lib, not a real process. The recount checks that one structure dominates before restructuring it.

    Diagram
    course.lib EXAMPLE areas (library units): NAND2 = 2, INV = 1, DFF = 8
    netlist count: 10 NAND2, 5 INV, 2 DFF
    NAND2 part = 10 x 2 = 20
    INV part   = 5 x 1 = 5
    DFF part   = 2 x 8 = 16
    total = 20 + 5 + 16 = 41 area units
    NAND2 share = 20 / 41 = 48.78%, INV share = 5 / 41 = 12.20%, DFF share = 16 / 41 = 39.02%
    48.78 + 12.20 + 39.02 = 100.00

    NAND2 logic plus flops carry nearly 88 percent here. A fix aimed elsewhere misses the bulk of the cost.

    Common mistakes

    Common pitfall

    Averaging slack across paths hides the failure. One deeply negative path fails the design while the average still looks comfortable, so always sort by the worst slack.

    Interview

    Likely probes: which report comes first and why.

    • Worst-path slack first, since it names the failing endpoints and the margin.

    • Area by cell type second, since it names the structure worth restructuring.

    • Fanout third, since it separates a weak driver from a genuinely deep path.

    Check yourself P2 has slack -1.8 ns over 9 levels while P3 has -0.9 ns over 5 levels. Which path do you debug first?

    P2. It is the worst violation, so it sets the verdict; P3 waits until P2 is classified.

    Check yourself A netlist holds 10 NAND2, 5 INV, and 2 DFF cells at areas 2, 1, and 8. What is the total area?

    20 plus 5 plus 16, which is 41 area units in the teaching library.

    Related topics

    • The QoR debug method

    • Reading netlists and reports

    • Structuring and buffering

    Previous

    120 / 139

    Next: Constraint Causes

    Up next

    Up nextConstraint Causes

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • RTL Structure Causes
    • Fanout, Black Boxes and Classifying Paths