Redundant logic computes something already known or something nobody reads. Duplicate gates, self-cancelling terms and undriven or unused nets all qualify.
Removal is safe because the visible function never changes. The tool still proves that with an assertion in the script below.
Pattern | Rewrite |
|---|---|
|
|
|
|
Two gates with identical inputs | One gate driving both loads |
Undriven net, unused gate output | Delete the net and the gate |
Yosys splits the work across small passes that run in sequence. Each pass handles one shape of redundancy.
Pass | Job |
|---|---|
opt_expr | Simplifies expressions: constant folding and identical-input reduction. |
opt_merge | Merges functionally identical cells into one. |
opt_clean | Deletes unused cells and wires. |
opt | General clean-up pass over the network. |
The script below builds two identical AND gates feeding one OR. After the passes one coarse $and cell remains and no $or cell, which the two assertions pin.
read_verilog <<EOV
module top(input a, b, output y);
wire t1 = a & b;
wire t2 = a & b;
assign y = t1 | t2;
endmodule
EOV
hierarchy -check -top top
proc
opt_merge
opt_expr
opt
opt_clean
check
select -assert-count 1 t:$and
select -assert-none t:$or
stat
log PASS: duplicate AND merged and redundant OR goneRedundancy at RTL is not always redundancy at the gate level. Shared sub-expressions written twice in RTL merge only if every input matches exactly.
One AND gate. The duplicates merge and the OR of a signal with itself folds away.
It can. Different inputs mean no identical-input folding applies, so the OR keeps its function.