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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
    • Monitor & Driver Coding
    • Sequences Coding
    • TLM & Analysis
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
    • Env & Test Architecture
    • Debug Broken Testbench
      • Find config_db Mismatch
      • Find Objection Leak
      • Find TLM Null Port
      • Debug Tricky Q&A
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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‹Debug Broken Testbench
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. Debug Broken Testbench
  5. Debug Tricky Q&A

UVM Coding PracticeSenior

Debug Tricky Q&A

15 triage scenario interview questions.

On this page

    Q&A bank

    Debug triage interview bank.

    Sim hangs no UVM_ERROR?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Sim hangs no UVM_ERROR?
    
    A:
    Objection leak or driver wait forever — check objections and driver loop.
    
    FOLLOW-UP TRAP: Only waveform.

    No transactions on bus?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: No transactions on bus?
    
    A:
    Seq not started, null vif, wrong config path, driver not connected.
    
    FOLLOW-UP TRAP: Assume RTL dead.

    Duplicate UVM_ERROR reports?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Duplicate UVM_ERROR reports?
    
    A:
    Multiple subscribers or repeat compare — filter or fix source.
    
    FOLLOW-UP TRAP: Lower verbosity only.

    Factory wrong type created?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Factory wrong type created?
    
    A:
    factory debug — override order or new() bypass.
    
    FOLLOW-UP TRAP: Recompile only.

    config_db get fails?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: config_db get fails?
    
    A:
    dump config_db — path typo or set after get phase.
    
    FOLLOW-UP TRAP: Random set path.

    TLM null port?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: TLM null port?
    
    A:
    connect not called or wrong export — print topology.
    
    FOLLOW-UP TRAP: Assume monitor broken.

    Scoreboard mismatch every cycle?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Scoreboard mismatch every cycle?
    
    A:
    Compare too early or wrong field — check FIFO policy.
    
    FOLLOW-UP TRAP: Change expected values randomly.

    Random different every run?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Random different every run?
    
    A:
    Seed not controlled — plusarg + set_rand_seed.
    
    FOLLOW-UP TRAP: Disable random.

    Regression triage order?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Regression triage order?
    
    A:
    Repro seed → log delta → waveform last.
    
    FOLLOW-UP TRAP: Wave first always.

    UVM_HIGH flood?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: UVM_HIGH flood?
    
    A:
    Verbosity id filter — fix source not global NONE.
    
    FOLLOW-UP TRAP: Hide all messages.

    Phase never ends?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Phase never ends?
    
    A:
    Objection trace — who raised?
    
    FOLLOW-UP TRAP: Kill sim from script.

    Driver item_done missing?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Driver item_done missing?
    
    A:
    Sequencer hang — classic junior bug.
    
    FOLLOW-UP TRAP: Restart seq only.

    Two tests conflict?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Two tests conflict?
    
    A:
    Shared cfg in config_db not cleared — fresh test instance.
    
    FOLLOW-UP TRAP: Same env state.

    RAL mirror wrong?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: RAL mirror wrong?
    
    A:
    predict after write; adapter byte lanes.
    
    FOLLOW-UP TRAP: Manual mirror everywhere.

    Interview debug scenario?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Interview debug scenario?
    
    A:
    Narrate hypothesis list before fix — structured triage.
    
    FOLLOW-UP TRAP: Jump to answer.
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    See also

    • Find config_db Mismatch
    • Find Objection Leak