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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
    • Monitor & Driver Coding
    • Sequences Coding
    • TLM & Analysis
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
    • Env & Test Architecture
    • Debug Broken Testbench
      • Find config_db Mismatch
      • Find Objection Leak
      • Find TLM Null Port
      • Debug Tricky Q&A
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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←Debug Broken Testbench
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. Debug Broken Testbench
  5. Find Objection Leak
On this page

    UVM Coding PracticeSenior

    Find Objection Leak

    Test hangs — missing drop_objection.

    Triage worksheet (say aloud before opening code)

    1. Symptom: Simulation hangs after UVM_TEST_DONE — no timeout, no UVM_ERROR

    2. Hypothesis list — config_db, objections, TLM connect, factory, seq not started

    3. Minimal experiment — dump, topology print, one UVM_INFO probe

    4. Root cause statement in one sentence

    5. Fix + regression hook

    Interview prompt

    Test hangs at end — walk objection debug before showing fix.

    Diagram
    WHITEBOARD CHAIN
    
    1. DECLARE    interfaces / types / ports you need
    2. SKELETON   class extends + utils macro + key methods
    3. MECHANISM  fill one critical method while narrating
    4. PITFALL    name one bug juniors make on this pattern
    5. TEST       how you would smoke-test the component

    Buggy snippet — critique verbally

    design.sv
    1
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    3
    4
    5
    task run_phase(uvm_phase phase);
      phase.raise_objection(this);
      seq.start(sqr);
      // missing drop_objection
    endtask

    Answer

    • Add drop_objection after seq.

    • Or seq raises — test should not double raise.

    • Check objection trace for stuck count.

    Smoke test (5 minutes)

    • Repro hang.

    • Add drop — sim ends.

    • Try drain_time if DUT pipelined.

    Code lab drill

    After reading, try Code lab exercise uvm-l9-bug-objection — topic reference: /topics/uvm/coding-practice/debug-broken-tb/find-objection-leak

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    See also

    • Debug Tricky Q&A