Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
    • Monitor & Driver Coding
    • Sequences Coding
    • TLM & Analysis
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
    • Env & Test Architecture
    • Debug Broken Testbench
      • Find config_db Mismatch
      • Find Objection Leak
      • Find TLM Null Port
      • Debug Tricky Q&A
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
Loading lesson

←Debug Broken Testbench
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. Debug Broken Testbench
  5. Find TLM Null Port
On this page

    UVM Coding PracticeSenior

    Find TLM Null Port

    Scoreboard never compares — connect missing.

    Triage worksheet (say aloud before opening code)

    1. Symptom: Scoreboard never compares — no SB UVM_INFO, act queue grows

    2. Hypothesis list — config_db, objections, TLM connect, factory, seq not started

    3. Minimal experiment — dump, topology print, one UVM_INFO probe

    4. Root cause statement in one sentence

    5. Fix + regression hook

    Interview prompt

    Scoreboard silent — TLM connect debug before fix.

    Diagram
    WHITEBOARD CHAIN
    
    1. DECLARE    interfaces / types / ports you need
    2. SKELETON   class extends + utils macro + key methods
    3. MECHANISM  fill one critical method while narrating
    4. PITFALL    name one bug juniors make on this pattern
    5. TEST       how you would smoke-test the component

    Buggy snippet — critique verbally

    design.sv
    // env connect_phase forgot:
    // agent.mon.ap.connect(sb.act_imp);

    Answer

    Connect analysis port in connect_phase; uvm_top.print_topology() to verify ap → imp.

    Mechanism to narrate

    • Unconnected analysis_port — write() never called

    • topology print shows dangling ports

    • connect in connect_phase not run_phase

    Smoke test (5 minutes)

    • After connect — one beat produces SB log.

    • topology shows mon.ap → sb.act_imp.

    Code lab drill

    After reading, try Code lab exercise uvm-l9-bug-tlm — topic reference: /topics/uvm/coding-practice/debug-broken-tb/find-tlm-null-port

    Previous

    231 / 280

    Next: Debug Tricky Q&A

    Up next

    Up nextDebug Tricky Q&A

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Find config_db Mismatch