RAL interview bank.
[INT][SENIOR][UVM-CODE]
Q: predict vs mirror?
A:
predict updates mirror without bus; read updates from bus.
FOLLOW-UP TRAP: Expect mirror match without predict after write.[INT][SENIOR][UVM-CODE]
Q: reg2bus direction?
A:
Convert reg item to bus txn for frontdoor.
FOLLOW-UP TRAP: bus2reg in reg2bus function.[INT][SENIOR][UVM-CODE]
Q: Byte enables on APB adapter?
A:
Map reg byte lane to pstrb from addr offset.
FOLLOW-UP TRAP: Always full strobe.[INT][SENIOR][UVM-CODE]
Q: Endianness in adapter?
A:
Match peripheral spec — swap bytes in reg2bus.
FOLLOW-UP TRAP: Assume little-endian DUT.[INT][SENIOR][UVM-CODE]
Q: Backdoor peek?
A:
hdl path peek — no bus, bypasses adapter.
FOLLOW-UP TRAP: Backdoor through adapter only.[INT][SENIOR][UVM-CODE]
Q: Frontdoor write flow?
A:
reg.write() → adapter reg2bus → driver → bus.
FOLLOW-UP TRAP: Skip adapter in interview sketch.[INT][SENIOR][UVM-CODE]
Q: Built-in reg sequence?
A:
uvm_reg_hw_reset_seq, bit bash — know names.
FOLLOW-UP TRAP: Hand-write every reg test.[INT][SENIOR][UVM-CODE]
Q: Reg map duplication?
A:
One map per address view — default map.
FOLLOW-UP TRAP: Two maps same addr conflict.[INT][SENIOR][UVM-CODE]
Q: Mem vs reg in RAL?
A:
uvm_mem for arrays; reg for control regs.
FOLLOW-UP TRAP: Reg for large memory space.[INT][SENIOR][UVM-CODE]
Q: Field access policy?
A:
RW, RO, WO — adapter respects WO on read.
FOLLOW-UP TRAP: Write RO field in test.[INT][SENIOR][UVM-CODE]
Q: Adapter bus width mismatch?
A:
Split 32-bit reg to 8-bit bus transactions.
FOLLOW-UP TRAP: Single beat always 32-bit.[INT][SENIOR][UVM-CODE]
Q: RAL reset values?
A:
Mirror reset from reg reset value; check post-reset.
FOLLOW-UP TRAP: Assume zero without spec.[INT][SENIOR][UVM-CODE]
Q: Reg predictor?
A:
Bus monitor → reg predictor → update mirror.
FOLLOW-UP TRAP: Manual mirror update everywhere.[INT][SENIOR][UVM-CODE]
Q: Whiteboard reg adapter 15 min?
A:
reg2bus + bus2reg + field mask + byte lane.
FOLLOW-UP TRAP: Full reg model first.[INT][SENIOR][UVM-CODE]
Q: RAL in scoreboard?
A:
Optional — compare reg mirror to expected.
FOLLOW-UP TRAP: RAL replaces scoreboard always.[INT][SENIOR][UVM-CODE]
Q: Multiple adapters?
A:
Per bus type or per reg map interface.
FOLLOW-UP TRAP: One adapter all protocols.[INT][SENIOR][UVM-CODE]
Q: Lock reg during test?
A:
Bus lock or exclude from random access.
FOLLOW-UP TRAP: Random hits lock reg.[INT][SENIOR][UVM-CODE]
Q: Coverage on reg fields?
A:
uvm_reg_field callbacks or cover in tests.
FOLLOW-UP TRAP: No field level coverage plan.[INT][SENIOR][UVM-CODE]
Q: Adapter error response?
A:
bus2reg maps error to UVM status.
FOLLOW-UP TRAP: Ignore slverr.[INT][SENIOR][UVM-CODE]
Q: 32-bit reg on 8-bit APB?
A:
Four byte transactions or sequential reads — state approach.
FOLLOW-UP TRAP: One APB beat for full 32.