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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
    • Monitor & Driver Coding
    • Sequences Coding
    • TLM & Analysis
      • Analysis Port Fanout
      • Blocking TLM FIFO
      • Subscriber Compare Hook
      • TLM Tricky Q&A
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
    • Env & Test Architecture
    • Debug Broken Testbench
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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←TLM & Analysis
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. TLM & Analysis
  5. TLM Tricky Q&A
On this page

    UVM Coding PracticeSenior

    TLM Tricky Q&A

    20 TLM/analysis interview questions.

    Q&A bank

    TLM interview bank.

    analysis_port vs analysis_export?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: analysis_port vs analysis_export?
    
    A:
    port initiates write(); export forwards to imp.
    
    FOLLOW-UP TRAP: Connecting port to port without export.

    Fanout multiple subscribers?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Fanout multiple subscribers?
    
    A:
    One analysis port can connect to multiple exports — broadcast.
    
    FOLLOW-UP TRAP: Expecting unconnected imp silent fail.

    uvm_tlm_fifo depth?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: uvm_tlm_fifo depth?
    
    A:
    Blocking put/get — depth 0 vs bounded affects backpressure.
    
    FOLLOW-UP TRAP: Unbounded fifo memory.

    write() reentrancy?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: write() reentrancy?
    
    A:
    Same thread usually; avoid heavy work in write — offload if needed.
    
    FOLLOW-UP TRAP: Blocking write chain deadlock.

    Subscriber vs scoreboard?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Subscriber vs scoreboard?
    
    A:
    Subscriber: light reaction. Scoreboard: compare state.
    
    FOLLOW-UP TRAP: Full compare in subscriber.

    blocking vs nonblocking TLM?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: blocking vs nonblocking TLM?
    
    A:
    blocking put/get handshake vs try_put.
    
    FOLLOW-UP TRAP: Wrong pairing port/export types.

    TLM fifo vs analysis?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: TLM fifo vs analysis?
    
    A:
    Fifo decouples producer/consumer rates; analysis is push.
    
    FOLLOW-UP TRAP: Fifo for broadcast — wrong pattern.

    analysis_imp macro?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: analysis_imp macro?
    
    A:
    uvm_analysis_imp_decl + write function per type.
    
    FOLLOW-UP TRAP: Wrong txn type parameter.

    Subscriber compare hook?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Subscriber compare hook?
    
    A:
    write() samples covergroup or checks one field.
    
    FOLLOW-UP TRAP: Entire protocol in subscriber.

    TLM in connect_phase?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: TLM in connect_phase?
    
    A:
    analysis_port.connect(subscriber.analysis_export);
    
    FOLLOW-UP TRAP: Connect in run_phase.

    Null analysis export?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Null analysis export?
    
    A:
    write not called — check connect and port name.
    
    FOLLOW-UP TRAP: Multiple connects to same imp wrongly.

    TLM across hierarchy?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: TLM across hierarchy?
    
    A:
    Connect at env level agent.monitor.ap to env.sb.act_imp.
    
    FOLLOW-UP TRAP: Cross-hierarchy illegal connect.

    uvm_subscriber pattern?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: uvm_subscriber pattern?
    
    A:
    extends uvm_subscriber#(txn) with write(txn).
    
    FOLLOW-UP TRAP: Forget analysis_export in base.

    Backpressure with fifo?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Backpressure with fifo?
    
    A:
    blocking put waits when fifo full.
    
    FOLLOW-UP TRAP: Nonblocking only and lose data.

    TLM recording?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: TLM recording?
    
    A:
    Optional record txn in write for debug.
    
    FOLLOW-UP TRAP: Record every field always — log flood.

    Analysis vs port in driver?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Analysis vs port in driver?
    
    A:
    Driver uses seq_item_port; monitor uses analysis_port — different.
    
    FOLLOW-UP TRAP: analysis for stimulus.

    Multi-txn type fanout?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Multi-txn type fanout?
    
    A:
    Separate analysis ports per type or generic subscriber.
    
    FOLLOW-UP TRAP: Type mismatch compile error.

    TLM performance?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: TLM performance?
    
    A:
    Avoid deep write chains; filter early.
    
    FOLLOW-UP TRAP: Scoreboard on every cycle tick.

    Whiteboard analysis fanout?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Whiteboard analysis fanout?
    
    A:
    monitor.ap → sb + cov + logger diagram in 5 min.
    
    FOLLOW-UP TRAP: No labels on arrows.

    TLM vs mailbox?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: TLM vs mailbox?
    
    A:
    UVM TLM standardized; mailbox SV primitive — prefer TLM in UVM TB.
    
    FOLLOW-UP TRAP: Mixing styles without reason.
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    See also

    • Analysis Port Fanout
    • Blocking TLM FIFO