Interview Q&A: Active vs Passive Agents

[INT][SENIOR][UVM] MODEL ANSWER

Q: Active vs passive agent?

A:
  MECHANISM:  Active = driver + sequencer + monitor. Passive = monitor only (no drive path).
  MOTIVATION:  Block TB drives pins; chip TB reuses VIP passive on RTL-master interfaces.
  WHEN:       cfg.is_active=UVM_ACTIVE at block; UVM_PASSIVE when RTL drives bus.
  PITFALL:    Two active masters on same bus at chip — bus fight, intermittent X.
  EXAMPLE:    Same axi_agent code; chip test sets cfg.is_active=UVM_PASSIVE before env.build.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Conditional build pattern?

A:
  MECHANISM:  agent build_phase: always create monitor; if (cfg.is_active == UVM_ACTIVE)
              create driver and sequencer; connect_phase wires drv only if active.
  MOTIVATION:  One agent class serves both modes — no forked passive variant code.
  WHEN:       Standard VIP pattern — is_active from config object via config_db.
  PITFALL:    Creating driver in passive mode 'just in case' — accidental enable risk.
  EXAMPLE:    if (cfg.is_active) begin drv=...create; sqr=...create; end

[INT][SENIOR][UVM] MODEL ANSWER

Q: Block → chip agent changes?

A:
  MECHANISM:  Flip is_active passive on interfaces now driven by RTL/CPU; keep monitors
              for scoreboard; add chip-level env scoreboard paths.
  MOTIVATION:  Reuse VIP economics — same agent, different cfg, no rewrite.
  PLAN:       Audit each interface: who is bus master at chip? Passive if RTL.
              End-to-end scb spans subtrees. Virtual seq for SW-like scenarios.
  PITFALL:    Leaving block active master on bus CPU now drives — classic integration bug.
  EXAMPLE:    PCIe EP agent passive at chip; root complex RTL drives; mon feeds fabric scb.

[INT][SENIOR][UVM] reuse ladder (whiteboard)

  BLOCK:      UVM_ACTIVE — agent drives, full block scb
  SUBSYSTEM:  mix active/passive per interface ownership
  CHIP:       mostly UVM_PASSIVE monitors + chip scb + vseqs

[INT][SENIOR][UVM] MODEL ANSWER

Q: Active + passive on same bus?

A:
  MECHANISM:  Multiple passive monitors OK (different observation points); only ONE
              active driver/master per shared bus unless multi-master protocol designed for it.
  MOTIVATION:  Bus is single shared resource — two drivers contend without arbitration design.
  WHEN:       Passive mon on RTL port + passive mon on VIP port — fine for cross-check.
  NOT WHEN:   Active VIP master + RTL master without explicit multi-master protocol support.
  PITFALL:    'Passive agent' with hidden driver still driving — cfg bug not mode bug.
  EXAMPLE:    Chip AXI: CPU RTL master + passive axi_mon; VIP active only in block TB.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Configuring is_active?

A:
  MECHANISM:  cfg object field is_active set in test build_phase before env.build;
              config_db::set to agent path; agent get in build and branch create.
  MOTIVATION:  Test controls integration mode without editing agent source.
  WHEN:       base_test sets default ACTIVE; chip_integration_test sets PASSIVE per agt.
  PITFALL:    Setting is_active after env.build — driver already exists.
  EXAMPLE:    uvm_config_db#(axi_cfg)::set(this,"env.axi_agt","cfg",passive_cfg);

[INT][SENIOR][UVM] MODEL ANSWER

Q: Sequences with passive agent?

A:
  MECHANISM:  Passive agent has no sequencer/driver — seq_lib not started on that agent.
              Stimulus comes from RTL or other active agents; passive mon observes.
  MOTIVATION:  Sequences require active path — passive is observe-only for that interface.
  WHEN:       Chip test starts vseq on active debug port; passive ports only monitored.
  PITFALL:    seq.start(passive_agt.sequencer) — null handle if passive build skipped sqr.
  EXAMPLE:    Chip vseq programs via JTAG active port; AXI traffic from CPU — AXI agent passive.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Verify passive mode?

A:
  MECHANISM:  print_topology shows no driver/sequencer; mon.ap has traffic; no vif
              output assignments from TB side; scb receives RTL-driven txns.
  MOTIVATION:  Confirm cfg applied before build — topology is ground truth.
  WHEN:       After chip integration bring-up; first test on reused VIP.
  PITFALL:    Mon silent because vif wrong hierarchy path — looks passive broken, is wiring bug.
  EXAMPLE:    end_of_elaboration: no drv in topology; mon prints txn count > 0 from CPU traffic.