Part 11 · Senior Prep · Intermediate

Interview Q&A: Agent Architecture

Model answers on agent wrapper role, standard child components, connect_phase wiring, analysis port fan-out, and architecture debug.

Wrapper and internals

Q: What is the role of a UVM agent?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Role of UVM agent?

A:
  MECHANISM:  Agent wraps one interface — monitor always, driver+sequencer if active,
              exports analysis_port for observed transactions.
  MOTIVATION:  Reusable boundary so env connects once; integrator uses cfg + seq_lib.
  WHEN:       Every protocol interface needing stimulus and/or observation.
  NOT WHEN:   Internal RTL tie-off with no external visibility — skip agent.
  PITFALL:    Env reaching into agt.drv.vif — bypasses encapsulation.
  EXAMPLE:    axi_agent: cfg.is_active gates drv/sqr build; mon.ap always wired to scb.

Q: What are the standard agent child components?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Standard agent internals?

A:
  MECHANISM:  monitor (always), sequencer + driver (active only), optional coverage
              subscriber, optional protocol checker inside agent.
  MOTIVATION:  Partition: mon observes DUT-visible truth; drv executes seq items;
              sqr arbitrates sequence requests.
  WHEN:       Canonical three-component active agent; passive = monitor + ap only.
  PITFALL:    Scoreboard inside agent — checking usually lives at env level.
  EXAMPLE:    pcie_agent: mon + drv + sqr + cfg; passive build skips drv/sqr create.

Q: What happens in agent connect_phase?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Agent connect_phase?

A:
  MECHANISM:  If active: drv.seq_item_port.connect(sqr.seq_item_export).
              Always: mon.ap.connect(agt.ap) or direct export of mon.ap as agt.ap.
  MOTIVATION:  Wiring after all build completes — endpoints exist, no null handles.
  WHEN:       Standard UVM — never connect in build_phase.
  PITFALL:    Connecting env to mon.ap before agent re-exports — fragile path.
  EXAMPLE:    agt.ap = mon.ap in connect; env connects scb to agt.ap not mon directly.

diagram

[INT][SENIOR][UVM] agent architecture whiteboard

  [AGT] axi_agent
    ├─ [MON] monitor.ap ──► agt.ap (export to env)
    ├─ [SEQ] sequencer ◄──► [DRV] driver  (active only)
    └─ cfg (is_active, timing knobs)

  ENV connect: agt.ap → scb.act_imp, cov.analysis_export

Key takeaways

Agent = monitor always + active path gated by cfg.is_active.
connect_phase wires drv↔sqr and exports mon.ap as agent observation point.
Env connects to agt.ap — not driver internals.

Common pitfalls

Building driver in passive mode — wastes sim, risks accidental drive.
TLM connect in build_phase — sibling may not exist yet.

Analysis fan-out and debug

Q: Why export analysis_port at agent level?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Agent-level analysis_port?

A:
  MECHANISM:  agt.ap re-exports mon.ap — env fans out to scb, cov, predictor.
  MOTIVATION:  Integrator connects once at agent boundary; monitor relocation invisible.
  WHEN:       Any env with multiple subscribers on same observed stream.
  PITFALL:    Env connects directly to mon.ap — breaks if monitor hierarchy changes.
  EXAMPLE:    env.connect: agt.ap.connect(scb.imp); agt.ap.connect(cov.analysis_export).

Q: How do you debug agent architecture failures?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Agent architecture debug?

A:
  MECHANISM:  Failures: null vif, missing connect, passive/active mismatch, no ap traffic.
  MOTIVATION:  Architecture bugs surface as 'no transactions' or 'bus fight' — classify first.
  STEPS:      1) print_topology in end_of_elaboration. 2) cfg.is_active vs expectation.
              3) vif get in build. 4) ap connected? 5) mon seeing pins?
  PITFALL:    Debugging scoreboard when monitor never connected — wiring not logic bug.
  EXAMPLE:    Passive agent at chip but cfg still UVM_ACTIVE — two masters on AXI bus.

Q: Should protocol checkers live inside the agent?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Checker inside agent?

A:
  MECHANISM:  Optional protocol SVA/checker component inside agent, fed by monitor stream
              or bound to vif — reports via analysis or uvm_report.
  MOTIVATION:  Protocol rules travel with VIP — integrator enables via cfg flag.
  WHEN:       Reusable VIP shipping protocol compliance; enable/disable per integration.
  NOT WHEN:   Block-specific functional check — belongs in env scoreboard.
  PITFALL:    Checker that modifies pins — checkers observe, drivers actuate.
  EXAMPLE:    axi_protocol_checker subscribes to mon.ap; cfg.enable_checker=0 at chip fast sim.

Q: Agent vs env — where does the scoreboard live?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Scoreboard in agent or env?

A:
  MECHANISM:  Agent checks protocol legality; env scoreboard compares end-to-end
              expected vs actual across agents/ref model.
  MOTIVATION:  Agent = interface-local; env = system-level checking composition.
  WHEN:       Protocol checker in agent; datapath scoreboard in env.
  PITFALL:    Block scoreboard inside agent — cannot compose at chip without duplication.
  EXAMPLE:    axi_agent has protocol checker; env has axi_mem_scb comparing read data.

Key takeaways

agt.ap is the stable integrator connection point for observation.
Architecture debug: topology → cfg → vif → connect → mon traffic.
Protocol check in agent; functional scoreboard at env.

Common pitfalls

Scoreboard inside agent — blocks chip-level end-to-end checking.
Skipping print_topology — fastest way to spot missing connect.

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