Interview Q&A: Protocol Patterns

[INT][SENIOR][UVM] MODEL ANSWER

Q: Valid/ready in driver?

A:
  MECHANISM:  Assert valid; wait until ready sampled high on appropriate clock edge;
              complete transfer; deassert or hold per protocol; then item_done.
  MOTIVATION:  DUT backpressure stalls driver — pull model naturally waits in drive task.
  WHEN:       AXI/APB/valid-ready streams — driver respects ready before completing item.
  PITFALL:    Completing item_done before transfer accepted — sequence races ahead of DUT.
  EXAMPLE:    AXI write: hold awvalid until awready; then complete address phase before item_done.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Monitor sample point?

A:
  MECHANISM:  Sample when both valid and ready true (handshake complete) unless protocol
              spec defines multi-cycle partial sampling for separate phases.
  MOTIVATION:  One txn per accepted beat — scoreboard and coverage count completed transfers.
  WHEN:       @(posedge clk) if (valid && ready) build txn and ap.write.
  PITFALL:    Sample on valid alone — counts rejected/backpressured beats as false txns.
  EXAMPLE:    AXI: separate aw/w/b channels — sample each channel at its handshake complete.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Protocol error injection?

A:
  MECHANISM:  err_driver extends base driver OR item.err_flag randomized in seq;
              drive task branches to violate spec (early valid drop, wrong wstrb).
  MOTIVATION:  Verify DUT error detection and recovery — positive test alone insufficient.
  WHEN:       Factory override to err_driver in dedicated err_test; not default regression.
  PITFALL:    Error injection in main driver without override — corrupts all regressions.
  EXAMPLE:    axi_err_driver: random early wvalid deassert; DUT must flag slverr or ignore safely.

[INT][SENIOR][UVM] valid/ready timeline (whiteboard)

  clk        __/^^\__/^^\__/^^\__
  valid      ______/^^^^^^^^\____
  ready      ^^^^^^^^\________/^^
  transfer   ^           ^ handshake complete (sample here)
             assert      both high

[INT][SENIOR][UVM] MODEL ANSWER

Q: Outstanding transactions?

A:
  MECHANISM:  Driver may issue address phase while data phase pending; track outstanding
              IDs in associative array; item_done when full txn complete per protocol rules.
  MOTIVATION:  AXI allows multiple outstanding — driver must model ID space and ordering.
  WHEN:       cfg.max_outstanding > 1; driver maintains per-ID state machine.
  PITFALL:    item_done at address phase only — sequence thinks write complete, data not sent.
  EXAMPLE:    AXI driver: item_done after bresponse for write; outstanding aw and w pipelines.

[INT][SENIOR][UVM] MODEL ANSWER

Q: X on bus during reset?

A:
  MECHANISM:  Monitor gates sampling: if (rst_n) sample; else skip or flush partial txn.
  MOTIVATION:  X on valid/ready during reset creates garbage txns in scoreboard.
  WHEN:       Reset assertion: disable sampling; deassert: wait stable cycle before enable.
  PITFALL:    Sample first cycle after reset deassert without idle check — glitch txn.
  EXAMPLE:    mon: wait 2 cycles post rst_n deassert before ap.write enabled.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Configurable driver delay?

A:
  MECHANISM:  cfg.min_gap/max_gap randomized between items; drive task inserts #delay
              or wait N clocks after item_done before next get_next_item processes.
  MOTIVATION:  Stress DUT under varied bandwidth; avoid always back-to-back unless test intent.
  WHEN:       cfg fields set from test; driver reads cfg in drive gap insertion.
  PITFALL:    Hard-coded #0 gap — unrealistic max bandwidth always — misses backpressure bugs.
  EXAMPLE:    cfg.min_gap=0 max_gap=10; driver repeat gap inside {[0:10]} between items.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Checker vs driver violation detect?

A:
  MECHANISM:  Checker/mon observes and uvm_error on spec violation; driver may avoid
              illegal drive but should not silently fix DUT violations.
  MOTIVATION:  Checker is independent witness — driver following seq may legally inject errors.
  WHEN:       Checker flags illegal inter-beat spacing; err_driver intentionally violates for DUT test.
  PITFALL:    Driver 'corrects' bad seq item silently — hides stimulus bug and DUT corner.
  EXAMPLE:    Checker fires on stable violation; err_test expects DUT error response not checker pass.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Whiteboard APB transfer?

A:
  MECHANISM:  Setup: psel, paddr, pwrite, pwdata. Access: penable. Complete: pready high.
  DRIVER:     Drives setup → enable → waits pready → item_done.
  MONITOR:    Sample {addr,data,write} when penable && pready.
  MOTIVATION:  Interview checks you know handshake phases and sample point.
  PITFALL:    Drawing monitor sample at setup phase — wrong txn boundary.
  EXAMPLE:    Narrate while drawing: 'item_done after pready, mon writes txn same cycle.'