Memory Bandwidth and Throughput Limits — Extended Case Study

Extended case study

A review is called because a workload regresses after a Memory Bandwidth and Throughput Limits change.

Background

A stable baseline existed until a Memory Hierarchy change improved one benchmark and regressed a product workload on Bandwidth waterfall + queue latency report.

Symptoms observed

• Regression in Bandwidth waterfall + queue latency report

• Sim vs silicon disagreement

• Pressure to revert or ship risk

Investigation timeline

1. Freeze tags

2. Reproduce

3. Cluster

4. Experiment

5. Validate

6. Memo

Root cause

A hidden assumption in Memory Bandwidth and Throughput Limits failed under an unrepresented workload phase.

Fix and validation

• Build per-hop bandwidth waterfall under synchronized sampling intervals.

• Identify first queue where latency spikes with demand growth.

• Inspect controller scheduling for turnaround and bank-conflict inefficiency.

• Audit NoC arbitration policy for read starvation or burst unfairness.

• Validate fix with sustained and bursty traffic patterns at multiple temperatures.

Lessons learned

• Workload coverage beats clever microarchitecture

• Every change needs rollback triggers

BANDWIDTH DELIVERY ANALYSIS
workload: training_inference_mix
core_demand_gbps: 164
llc_delivered_gbps: 141
noc_delivered_gbps: 123
dram_served_gbps: 118
dram_theoretical_gbps: 164
row_buffer_hit_rate_pct: 61
ctrl_avg_queue_cycles: 43
action: reduce write-drain threshold and rebalance NoC VC priorities for read bursts

Architecture deep dive

Cache hierarchy trades area and power for AMAT and bandwidth.

Concept diagram

MEMORY HIERARCHY

Core
 ├─ L1I / L1D  (cycles: 1-4, tiny, latency critical)
 ├─ L2         (cycles: 8-20, private or cluster)
 ├─ LLC / SLC  (shared, bandwidth + coherency point)
 ├─ NoC        (queueing + arbitration)
 └─ DRAM/HBM   (large penalty, high energy)

AMAT = hit_time + miss_rate × miss_penalty
But senior analysis also asks: MLP, bandwidth, QoS, and tail latency.

Metric graph

MISS PENALTY WATERFALL

L1 hit          ██  3 cyc
L2 hit          ████████  12 cyc
LLC hit         ███████████████  32 cyc
DRAM miss       ████████████████████████████████████  180 cyc

Small MPKI can still dominate if miss penalty is huge.

Metrics and artifacts

• MPKI per level

• L2/L3 bandwidth utilization

• replacement policy stats

• prefetch accuracy

Mini case study

Doubling L2 size reduces capacity misses but IPC improves only 3% because conflict misses dominate a shared workload. Fix data layout and false sharing before more SRAM.

Debug branches

• If MPKI high but bandwidth low, footprint may exceed capacity.

• If bandwidth saturated, coherency or DMA may be the real limit.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.