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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
    • Caches
    • Memory Bandwidth and Latency
      • Peak, Protocol and Workload Bandwidth
      • Little's Law, MLP and the Waterfall
      • Row Buffers and Controller Scheduling
      • Prefetch Accuracy, Coverage and Pollution
      • Counters, QoS and Debug
    • Virtual Memory and the TLB
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Memory Bandwidth and Latency
  1. Topics
  2. Computer Architecture
  3. Memory Hierarchy
  4. Memory Bandwidth and Latency
  5. Peak, Protocol and Workload Bandwidth

Computer Architecture · All levels

Peak, Protocol and Workload Bandwidth

Headline, protocol and workload bandwidth with a worked efficiency decomposition.

On this page

    Three bandwidths

    Headline bandwidth is width times rate. It is the datasheet number and no workload reaches it.

    Protocol bandwidth subtracts overhead: address phases, headers, turnarounds and refresh. Workload bandwidth further subtracts access-pattern losses such as row conflicts and short bursts.

    Bandwidth

    Definition

    Example

    Headline

    Width × transfer rate

    128-bit AXI at 1 GHz is 16 GB/s

    Protocol

    Headline minus overhead

    Bursts and headers leave about 12.8 GB/s

    Workload

    Protocol minus pattern loss

    Stream mix delivers about 9.8 GB/s

    A worked decomposition

    Delivered bandwidth factors into five stated terms. Each term is measured or assumed, never borrowed from a datasheet alone.

    Diagram
    delivered = peak x burst_eff x (1 - AR_stall) x (1 - R_stall) x sched_eff
    peak:       128 bit = 16 B; 16 B x 1.0 GHz = 16.0 GB/s
    burst_eff:  0.80  -> 16.0 x 0.80 = 12.8 GB/s
    AR_stall:   0.10  -> 12.8 x 0.90 = 11.52 GB/s
    R_stall:    0.05  -> 11.52 x 0.95 = 10.944 GB/s
    sched_eff:  0.90  -> 10.944 x 0.90 = 9.8496 ~ 9.8 GB/s

    The DRAM side uses the same shape. Two DDR4-3200 channels give 2 × 8 B × 3200 MT/s, which is 51.2 GB/s headline, and 70 percent stream efficiency leaves about 36 GB/s.

    Options and their limits

    Each fix helps only the term it targets. Widening the bus never fixes a scheduler stall.

    Option

    Helps when

    Cost or limit

    Wider interface

    Bursts are long and the bus is the bottleneck

    Area and power of wider datapaths

    Deeper outstanding queues

    Latency hides behind parallelism (see next lesson)

    Buffer area and reorder complexity

    Smarter scheduling

    Bank conflicts and turnarounds dominate

    Starvation risk without fairness guards

    Prefetching

    Accesses are predictable and timely

    Wasted bytes and cache pollution

    Common mistakes

    Common pitfall

    Quoting headline bandwidth as available bandwidth overstates delivery by 30 to 50 percent on ordinary mixes. Always attach a number to a stated burst length, stall fraction and scheduler efficiency.

    Interview

    Likely probe: why did doubling bus width gain almost nothing? Answer with the decomposition: width scales peak, but the AR-stall and scheduler terms did not move, so delivered barely changed.

    Check yourself A 128-bit 1 GHz AXI port moves 64-byte bursts at 80 percent burst efficiency with no stalls. What is delivered?

    16 GB/s headline times 0.80 is 12.8 GB/s. The stall and scheduler terms are 1.0 here by statement.

    Check yourself Widening the bus from 64 to 128 bits raised measured bandwidth 8 percent. What does that imply?

    The bus was not the binding term. Some stall or scheduler term dominates, so profile the breakdown before spending more area.

    Related topics

    • Roofline and tuning

    • Little's law, MLP and the waterfall

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    See also

    • Row Buffers and Controller Scheduling
    • Prefetch Accuracy, Coverage and Pollution
    • Counters, QoS and Debug