Computer Architecture · All levels

Memory Bandwidth and Throughput Limits — Reports & Metrics

Reports & Metrics for Memory Bandwidth and Throughput Limits (Memory Hierarchy).

On-call / interview prompt

Which report lines prove Memory Bandwidth and Throughput Limits is healthy vs failing?

diagram

ARCHITECTURE ANALYSIS CHAIN

1. METRIC     — IPC, CPI, MPKI, bandwidth, latency, queue depth, stall cycles
2. HYPOTHESIS — microarch or system cause ordered by likelihood
3. EXPERIMENT — trace, PMU counter, simulation, or RTL probe
4. CHANGE      — pipeline, cache, NoC, or memory hierarchy adjustment
5. VALIDATION  — workload replay, regression suite, PPA impact

Reports to inspect

End-to-end bandwidth waterfall report by hierarchy stage
Memory controller queue occupancy and turnaround stats
NoC congestion and virtual-channel utilization map
Row-buffer hit/miss and bank-conflict analysis

diagram

BANDWIDTH DELIVERY ANALYSIS
workload: training_inference_mix
core_demand_gbps: 164
llc_delivered_gbps: 141
noc_delivered_gbps: 123
dram_served_gbps: 118
dram_theoretical_gbps: 164
row_buffer_hit_rate_pct: 61
ctrl_avg_queue_cycles: 43
action: reduce write-drain threshold and rebalance NoC VC priorities for read bursts

Smoke check (5 minutes)

Can you name the single worst line in the report?
Can you tie that line to a workload phase, structure, master, or data movement pattern?

How to read this like an architecture lead

The report is not a pass/fail artifact; it is a prioritization tool. Read Bandwidth waterfall + queue latency report by severity, locality, trend, and fix cost before touching the design.

Report triage order

Confirm workload, model tag, seed, counter definitions, and warmup window.
Separate product blockers from exploratory tuning opportunities.
Cluster failures by workload phase, master, cache level, NoC path, coherency state, or accelerator kernel.
Compare against previous tag to identify new regressions, not just absolute failures.
Translate the worst line into an owner, experiment, and rollback plan.

diagram

SENIOR REPORT READOUT
  worst_line: <copy exact report line>
  cluster: <workload phase / master / cache level / NoC path / coherency state>
  delta_from_previous: <new/worse/better/same>
  first_experiment: <cheap evidence-gathering action>
  decision: <change design / assign owner / keep risk with approval / stop release>

Metric graph to sketch in review

diagram

REPORT GRAPH — Bandwidth waterfall + queue latency report

stall contribution (% cycles)

frontend      ████████████  24
backend       ██████████████████  36
memory        ████████████████████████  48
fabric/qos    ████████  16
coherency     ██████████  20

How to read:
  1. Identify the dominant bar, not the noisiest anecdote.
  2. Cross-check with at least one independent artifact: trace, PMU, sim log, or waveform.
  3. If the dominant bar does not match the proposed fix, stop and reform the hypothesis.

Trend graph

diagram

METRIC TREND GRAPH — Memory Bandwidth and Throughput Limits

IPC / throughput
  ^
  |                  target
  |                 ─ ─ ─ ─ ─ ─ ─
  |            ● after bounded fix
  |         /
  |    ● baseline
  |  /
  |● failing run
  +---------------------------------> experiment index
    bad tag       hypothesis        accepted fix

Readout rule:
  - one dot is not a conclusion
  - compare against same workload, seed, model tag, and counter setup
  - explain why the fix moved the metric, not just that it moved

Architecture deep dive

Cache hierarchy trades area and power for AMAT and bandwidth.

Concept diagram

diagram

MEMORY HIERARCHY

Core
 ├─ L1I / L1D  (cycles: 1-4, tiny, latency critical)
 ├─ L2         (cycles: 8-20, private or cluster)
 ├─ LLC / SLC  (shared, bandwidth + coherency point)
 ├─ NoC        (queueing + arbitration)
 └─ DRAM/HBM   (large penalty, high energy)

AMAT = hit_time + miss_rate × miss_penalty
But senior analysis also asks: MLP, bandwidth, QoS, and tail latency.

Metric graph

diagram

MISS PENALTY WATERFALL

L1 hit          ██  3 cyc
L2 hit          ████████  12 cyc
LLC hit         ███████████████  32 cyc
DRAM miss       ████████████████████████████████████  180 cyc

Small MPKI can still dominate if miss penalty is huge.

Metrics and artifacts

MPKI per level
L2/L3 bandwidth utilization
replacement policy stats
prefetch accuracy

Mini case study

Doubling L2 size reduces capacity misses but IPC improves only 3% because conflict misses dominate a shared workload. Fix data layout and false sharing before more SRAM.

Debug branches

If MPKI high but bandwidth low, footprint may exceed capacity.
If bandwidth saturated, coherency or DMA may be the real limit.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

Connect every architecture claim to a workload and measurable metric.
State verification and PPA impact before proposing design changes.

Common pitfalls

Feature-driven design without MPKI/IPC/bandwidth evidence.
Ignoring coherency and NoC traffic in cache and accelerator sizing.

Read the numbers

Practice this lesson