VLSI DV Interview Puzzles · All levels

Sampling region off-by-one on state bins

Team expects bins 1,2,3 after three clocks but report differs. Compute actual hits and explain.

Puzzle

Difficulty: Medium · Puzzle 1 of 6 · Topic: Coverage Closure and Sampling Timing Puzzles

Team expects bins 1,2,3 after three clocks but report differs. Compute actual hits and explain.

Code

systemverilog
bit clk;
bit [1:0] state;

covergroup cg_evt @(posedge clk);
  cp_state: coverpoint state {
    bins s0 = {0};
    bins s1 = {1};
    bins s2 = {2};
    bins s3 = {3};
  }
endgroup

cg_evt c = new();

always_ff @(posedge clk)
  state <= state + 1;

initial begin
  state = 0;
  repeat (3) @(posedge clk);
end

Hint

Event sampling happens before NBA updates from always_ff.

Step-by-step solution

diagram
1) On each posedge, covergroup samples current state in active region.
2) state update uses NBA, so sampled values are pre-update.
3) Across three clocks from initial 0, sampled values are 0,1,2.
4) Hit bins are s0,s1,s2 -> 3/4 = 75%.

Answer

Answer: Actual coverage is 75% because sampled states are 0,1,2 (not 1,2,3).

Why candidates get it wrong

Waveform cursors often show post-NBA values, which can mislead coverage root-cause analysis.

Interviewer follow-up

What monitor timing change would capture post-update states without modifying DUT logic?

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