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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
    • Covergroup and Coverpoint Puzzles
    • Cross Coverage Puzzles
    • Coverage Options Puzzles
    • Coverage Closure and Sampling Timing Puzzles
      • Sampling region off-by-one on state bins
      • Unreachable bin from stimulus constraints
      • Manual sample called at wrong phase
      • get_coverage vs get_inst_coverage interpretation
      • Unreachable cross tuple from protocol rules
      • at_least threshold causes closure plateau
    • Functional Coverage Puzzles: Tricky Q&A
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Coverage Closure and Sampling Timing Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Functional Coverage Puzzles
  4. Coverage Closure and Sampling Timing Puzzles
  5. at_least threshold causes closure plateau

VLSI DV Interview Puzzles · All levels

at_least threshold causes closure plateau

Bins are touched but report remains 50%. Compute exact status and next action.

On this page

    Puzzle

    Difficulty: Medium · Puzzle 6 of 6 · Topic: Coverage Closure and Sampling Timing Puzzles

    Bins are touched but report remains 50%. Compute exact status and next action.

    Code

    design.sv
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    covergroup cg with function sample(bit [1:0] latency);
      cp_lat: coverpoint latency {
        option.at_least = 5;
        bins fast = {1};
        bins slow = {2};
      }
    endgroup
    
    initial begin
      cg c = new();
      repeat (5) c.sample(1);
      repeat (2) c.sample(2);
    end

    Hint

    Touch count is not enough; threshold controls covered/not-covered state.

    Step-by-step solution

    Diagram
    1) fast bin has 5 hits so it is covered.
    2) slow bin has 2 hits, below at_least=5, so not covered.
    3) Covered bins are 1 of 2 -> 50%.
    4) Need 3 more slow samples to close cp_lat to 100%.

    Answer

    Answer: Coverage is 50% because only fast meets threshold. slow needs 3 more hits.

    Why candidates get it wrong

    Debug logs can mislead when they show both values occurred but not how often relative to threshold.

    Interviewer follow-up

    How would you bias constraint distributions to close slow without overfitting stimulus?

    Related topics

    • Back to Coverage Closure and Sampling Timing Puzzles

    • Functional Coverage Puzzles section

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    Next: Functional Coverage Puzzles: Tricky Q&A

    Up next

    Up nextFunctional Coverage Puzzles: Tricky Q&A

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    See also

    • Sampling region off-by-one on state bins
    • Unreachable bin from stimulus constraints
    • Manual sample called at wrong phase