VLSI DV Interview Puzzles · All levels

at_least threshold causes closure plateau

Bins are touched but report remains 50%. Compute exact status and next action.

Puzzle

Difficulty: Medium · Puzzle 6 of 6 · Topic: Coverage Closure and Sampling Timing Puzzles

Bins are touched but report remains 50%. Compute exact status and next action.

Code

systemverilog
covergroup cg with function sample(bit [1:0] latency);
  cp_lat: coverpoint latency {
    option.at_least = 5;
    bins fast = {1};
    bins slow = {2};
  }
endgroup

initial begin
  cg c = new();
  repeat (5) c.sample(1);
  repeat (2) c.sample(2);
end

Hint

Touch count is not enough; threshold controls covered/not-covered state.

Step-by-step solution

diagram
1) fast bin has 5 hits so it is covered.
2) slow bin has 2 hits, below at_least=5, so not covered.
3) Covered bins are 1 of 2 -> 50%.
4) Need 3 more slow samples to close cp_lat to 100%.

Answer

Answer: Coverage is 50% because only fast meets threshold. slow needs 3 more hits.

Why candidates get it wrong

Debug logs can mislead when they show both values occurred but not how often relative to threshold.

Interviewer follow-up

How would you bias constraint distributions to close slow without overfitting stimulus?

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