VLSI DV Interview Puzzles · All levels
Unreachable bin from stimulus constraints
Why does this coverpoint plateau at 75% forever, and what is the correct closure action?
Puzzle
Difficulty: Easy · Puzzle 2 of 6 · Topic: Coverage Closure and Sampling Timing Puzzles
Why does this coverpoint plateau at 75% forever, and what is the correct closure action?
Code
systemverilog
class tr;
rand bit [1:0] opcode;
constraint legal_c { opcode inside {[0:2]}; }
endclass
covergroup cg with function sample(bit [1:0] opcode);
cp_opcode: coverpoint opcode {
bins op0 = {0};
bins op1 = {1};
bins op2 = {2};
bins op3 = {3};
}
endgroupHint
Check whether op3 can ever be generated under legal_c.
Step-by-step solution
diagram
1) Constraint legal_c allows only 0,1,2.
2) Bin op3 is unreachable by construction.
3) Maximum achievable legal hit bins are 3 of 4 -> 75% ceiling.
4) Closure fix is to align coverage model with stimulus/spec (ignore or remove op3, or broaden legal space intentionally).Answer
Answer: Coverage ceiling is 75% because op3 is unreachable. This is a model mismatch, not a random stimulus deficiency.
Why candidates get it wrong
Teams often burn regression time trying to close a mathematically unreachable bin.
Interviewer follow-up
What evidence would you include in a waiver request for op3?