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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
    • Covergroup and Coverpoint Puzzles
    • Cross Coverage Puzzles
    • Coverage Options Puzzles
    • Coverage Closure and Sampling Timing Puzzles
      • Sampling region off-by-one on state bins
      • Unreachable bin from stimulus constraints
      • Manual sample called at wrong phase
      • get_coverage vs get_inst_coverage interpretation
      • Unreachable cross tuple from protocol rules
      • at_least threshold causes closure plateau
    • Functional Coverage Puzzles: Tricky Q&A
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Coverage Closure and Sampling Timing Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Functional Coverage Puzzles
  4. Coverage Closure and Sampling Timing Puzzles
  5. Manual sample called at wrong phase

VLSI DV Interview Puzzles · All levels

Manual sample called at wrong phase

Manual sampling is used, but closure still misses the latest state. Compute observed bins and explain timing.

On this page

    Puzzle

    Difficulty: Hard · Puzzle 3 of 6 · Topic: Coverage Closure and Sampling Timing Puzzles

    Manual sampling is used, but closure still misses the latest state. Compute observed bins and explain timing.

    Code

    design.sv
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    bit clk;
    bit [1:0] state, next_state;
    
    covergroup cg with function sample(bit [1:0] s);
      cp_state: coverpoint s {
        bins s0 = {0};
        bins s1 = {1};
        bins s2 = {2};
        bins s3 = {3};
      }
    endgroup
    
    cg c = new();
    
    always_ff @(posedge clk) state <= next_state;
    always @(posedge clk) c.sample(state);
    
    initial begin
      state = 0;
      next_state = 1;
      @(posedge clk); next_state = 2;
      @(posedge clk); next_state = 3;
      @(posedge clk);
    end

    Hint

    sample(state) in an always block at posedge still reads pre-NBA state.

    Step-by-step solution

    Diagram
    1) c.sample(state) executes in active region on posedge.
    2) state <= next_state updates in NBA after active region.
    3) Sampled states over three edges are 0,1,2.
    4) Hit bins are s0,s1,s2 -> 3/4 = 75%, leaving s3 uncovered.

    Answer

    Answer: Observed closure is 75% because manual sample timing still captures old state values.

    Why candidates get it wrong

    Using sample() does not automatically fix timing; call site region still controls observed value.

    Interviewer follow-up

    Would clocking-block input skew or monitor-after-NBA sampling be a cleaner fix here?

    Related topics

    • Back to Coverage Closure and Sampling Timing Puzzles

    • Functional Coverage Puzzles section

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    See also

    • Sampling region off-by-one on state bins
    • Unreachable cross tuple from protocol rules
    • at_least threshold causes closure plateau