VLSI DV Interview Puzzles · All levels
Manual sample called at wrong phase
Manual sampling is used, but closure still misses the latest state. Compute observed bins and explain timing.
Puzzle
Difficulty: Hard · Puzzle 3 of 6 · Topic: Coverage Closure and Sampling Timing Puzzles
Manual sampling is used, but closure still misses the latest state. Compute observed bins and explain timing.
Code
systemverilog
bit clk;
bit [1:0] state, next_state;
covergroup cg with function sample(bit [1:0] s);
cp_state: coverpoint s {
bins s0 = {0};
bins s1 = {1};
bins s2 = {2};
bins s3 = {3};
}
endgroup
cg c = new();
always_ff @(posedge clk) state <= next_state;
always @(posedge clk) c.sample(state);
initial begin
state = 0;
next_state = 1;
@(posedge clk); next_state = 2;
@(posedge clk); next_state = 3;
@(posedge clk);
endHint
sample(state) in an always block at posedge still reads pre-NBA state.
Step-by-step solution
diagram
1) c.sample(state) executes in active region on posedge.
2) state <= next_state updates in NBA after active region.
3) Sampled states over three edges are 0,1,2.
4) Hit bins are s0,s1,s2 -> 3/4 = 75%, leaving s3 uncovered.Answer
Answer: Observed closure is 75% because manual sample timing still captures old state values.
Why candidates get it wrong
Using sample() does not automatically fix timing; call site region still controls observed value.
Interviewer follow-up
Would clocking-block input skew or monitor-after-NBA sampling be a cleaner fix here?