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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
    • Global and Detailed Routing Convergence
    • Antenna Rules and Corrective Strategies
    • Metal Layer Planning and Capacity Management
    • Shielding, Tie Cells, and Signal Hygiene
    • Via Planning and Via Ladder Reliability
    • Route-Driven Timing Optimization
    • Special Nets and Power Routing Strategy
    • Routing DRC Debug and Forensic Workflow
      • Routing DRC Debug and Forensic Workflow — Mechanism
      • Routing DRC Debug and Forensic Workflow — Inputs & Outputs
      • Routing DRC Debug and Forensic Workflow — Reports & Metrics
      • Routing DRC Debug and Forensic Workflow — Debug Playbook
      • Routing DRC Debug and Forensic Workflow — Worked Example
      • Routing DRC Debug and Forensic Workflow — Pitfalls & Red Flags
      • Routing DRC Debug and Forensic Workflow — Interview Drills
      • Routing DRC Debug and Forensic Workflow — Review Checklist
    • Routing Tricky Q&A
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Routing DRC Debug and Forensic Workflow
  1. Topics
  2. Physical Design
  3. Routing
  4. Routing DRC Debug and Forensic Workflow
  5. Routing DRC Debug and Forensic Workflow — Worked Example

Physical Design · All levels

Routing DRC Debug and Forensic Workflow — Worked Example

Worked Example for Routing DRC Debug and Forensic Workflow (Routing).

On this page

    Scenario

    A block encounters a Routing DRC Debug and Forensic Workflow issue during late implementation.

    Timeline

    1. Metric fails at review meeting

    2. Engineer captures report and layout snapshot

    3. Root cause traced to incorrect assumption from prior stage

    4. Minimal fix applied and documented

    5. Signoff matrix re-run on tagged database

    Outcome

    Closure restored with documented risk and regression proof.

    Senior debrief

    After solving the example, write the debrief a lead would expect: what changed, why it worked, what could regress, and what permanent methodology update prevents recurrence.

    Diagram
    STAFF REVIEW MEMO — Routing / Routing DRC Debug and Forensic Workflow
    
    1. Current state
       - Failing / watched metric: Routing closure dashboard
       - Database tag, corner/mode, tool version: <fill before review>
       - Physical scope: block, hierarchy, macro region, clock domain, or net class
    
    2. Root-cause hypothesis
       - Most likely mechanism: <name physical or constraint mechanism>
       - Competing hypothesis: <name the second plausible cause>
       - Evidence still missing: <report/map/schematic/check>
    
    3. Proposed action
       - Minimal reversible fix: <physical, constraint, ECO, or methodology change>
       - Expected improvement: <metric delta>
       - Regression risk: Ad-hoc DRC cleanup can stall tapeout and mask root-cause failures.
    
    4. Regression and signoff
       - Re-run: Routing closure dashboard
       - Must not regress: PV signoff and tapeout readiness depend on forensic-grade DRC closure.
       - Decision owner: PD owner

    Deep dive: how this shows up in real closure

    Routing decides whether the placed design is manufacturable and extractable.

    Reports and artifacts to inspect

    • global route overflow by layer and region

    • detailed route DRC/DRV summary grouped by rule

    • antenna report: gate area, metal area, ratio, suggested diode

    • post-route extraction delta on critical nets

    Mini case study

    Detailed route completes with 4,000 spacing violations around a macro channel. The design is not 'routed'. Cluster by rule and region, fix the channel or layer plan, then re-route locally.

    Debug branches

    • If antenna violations cluster on long lower-metal routes, jump to upper metal earlier or insert diode cells.

    • If via violations dominate, inspect via arrays and preferred via stacks, especially on power transitions.

    • If crosstalk worsens timing, space, shield, or layer-promote the victim nets.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Routing decides whether the placed design is manufacturable and extractable. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

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    See also

    • Routing DRC Debug and Forensic Workflow — Mechanism
    • Routing DRC Debug and Forensic Workflow — Inputs & Outputs
    • Routing DRC Debug and Forensic Workflow — Reports & Metrics