Before signoff, exercise representative concurrent traffic with production-like initialisation. Trace each applicable bridge transformation—width, ID, burst, address and attributes—and verify clock-domain crossings using a protocol-aware structure whose reset, capacity and backpressure contract has been checked; an asynchronous FIFO is one common implementation, not the only possible architecture.
Place progress/timeout monitoring at useful boundaries with thresholds and recovery defined by system service assumptions; base AXI itself sets no universal response deadline.
Interconnect route table must match firmware memory map.
Power domain crossings need isolation — not just clock domain.