Core concepts

Unified high-speed debug methodology

Cover link state (up/down, speed, width), error counters, PHY margin, packet/frame evidence and software configuration. The useful order depends on available observation points; preserve the same traffic interval and transaction context instead of treating the list as a verdict hierarchy.

Narrow physical margin is evidence to investigate, not proof that RTL, clocks or software configuration are correct. Confirm counter definitions, traffic and test duration; compare channel, receiver settings and interface timing with a known-good case. Treat each controlled experiment as evidence for or against a hypothesis.

HIGH-SPEED DEBUG STACK

app/driver --> MAC/framing --> PCS/encoding --> SerDes/PHY --> channel
     |              |               |                |
  SW trace      pkt counters    block lock       eye/BER/margin

Key takeaways

• Draw the diagram before reading waveforms.

• Name the transaction ID on every debug step.