Primary debug scenario

Symptom: 100G Ethernet works on eval board. 40% throughput on product with CRC errors.

Triage steps

1. Compare PHY per-lane margin: eval vs product.

2. Compare package/board channel models and measured configuration against the eval path.

3. Check if all lanes have similar margin — one outlier?

4. Try lower speed — does CRC clean up?

5. Correlate MAC/PCS/PHY counters, clocks, resets, lane mapping, receiver settings and identical traffic before assigning the board as cause.

Common pitfalls

• Picking maximum or geometric-centre EQ without a cornered sweep.

• Treating CRC/FCS errors as proof of a PHY fault.

• Ignoring temperature corner testing.