Low Power (LP) mode: single-ended, slow, for control and escape commands. High Speed (HS) mode: differential, fast, for image/display data. Transition LP→HS for each burst.
In the conventional D-PHY example here, a clock lane accompanies high-speed data lanes. Lane count, supported lane rate and packet overhead bound payload capacity. This is not a universal lane diagram for CSI-2: C-PHY and other supported mappings have different physical signalling. Select the actual protocol/PHY revisions before defining wire-level serialization or packed-pixel byte order.
MIPI CSI-2 BURST
LP: [SoT] ---- HS burst (image line data) ---- [EoT] LP:
^ ^
start of end of
transmission transmissionFor the conventional CSI-2 packet example, long packets carry a header including data type and word count, payload and payload CRC; short packets carry frame synchronisation information. Frame Start and Frame End delimit the example frame, while Line Start and Line End packets are optional in the referenced CSI-2 receiver example (Microchip UG0763 revision 1.0). Do not import DSI video timing names as universal CSI-2 packet names.
Check the sensor's complete frame schedule and the receiver's line, buffering and service contract. Blanking, packet bursts and downstream memory service all affect capacity. Frame drops are a symptom with several possible causes, not proof of insufficient blanking alone.
Virtual channels multiplex multiple data streams on same lanes.
RAW, RGB, YUV formats differ in bits-per-pixel and packing.
Lane remapping or polarity correction is implementation-dependent; verify supported wiring and configuration at both ends.
Virtual channels multiplex multiple data streams on same lanes.
RAW, RGB, YUV formats differ in bits-per-pixel and packing.
Lane remapping or polarity correction is implementation-dependent; verify supported wiring and configuration at both ends.