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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
      • MIPI CSI / DSI Overview: Concepts
      • MIPI CSI / DSI Overview: Integration
      • MIPI CSI / DSI Overview: Debug
      • MIPI CSI / DSI Overview: Interview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←MIPI CSI / DSI Overview
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. MIPI CSI / DSI Overview
  5. MIPI CSI / DSI Overview: Debug
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    Interface ProtocolsAll levels

    MIPI CSI / DSI Overview: Debug

    Debug for MIPI CSI / DSI Overview.

    Primary debug scenario

    Symptom: Camera preview shows frame drops every few seconds. Lane errors in PHY status.

    Triage steps

    1. Check lane error counter — which lane? Continuous or burst?

    2. Verify lane speed vs board SI capability.

    3. Check blanking budget — is sensor outputting too fast?

    4. PHY: LP→HS transition timing meets spec?

    5. For a lower-rate experiment, reduce the offered image/frame rate to fit the new lane capacity and configure both ends consistently.

    Common pitfalls

    • Frame drops from insufficient blanking, not just SI.

    • Assuming corruption versus dropped frames uniquely identifies a wiring or formatting fault.

    • Sensor format mismatch with receiver config.

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    See also

    • MIPI CSI / DSI Overview: Concepts