Transaction Layer (TL): TLPs carry the actual request — memory read/write, config access, message. Each TLP has a header (type, length, address/requester ID) and optional payload.
For the conventional non-Flit PCIe examples in this overview, the Data Link Layer uses sequence numbers, link CRC and ACK/NAK with replay of unacknowledged TLPs. Link retry improves delivery reliability within its supported conditions; it is not a guarantee against every persistent fault. Newer Flit-mode mechanisms require their own revision-specific treatment.
The Physical Layer handles link training, lanes and electrical signalling. PCIe Gen1/Gen2 use 8b/10b; Gen3–Gen5 use 128b/130b. Do not extend this encoding summary to every later generation.
PCIe LAYER STACK
Application (driver)
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Transaction Layer: TLP (MemRd, MemWr, CplD, CfgRd)
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Data Link Layer: seq#, CRC, ACK/NAK, replay
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Physical Layer: LTSSM, lanes, encoding, EQPCIe uses credit-based flow control. The receiver advertises buffer space per TLP type (Posted, Non-Posted, Completion). The sender cannot issue a TLP until it has credits. Credit exhaustion looks like a hang but is really backpressure.
Completion credits are separate from request credits. A common bug: request credits available but completion credits exhausted — reads hang waiting for completion buffer space.
Track Posted, Non-Posted and Completion traffic with their header/data credit accounting for the selected virtual channel; one scalar TLP count is not a complete credit model.
Credit update uses DLLPs — not visible as TLPs.
Switch ports have independent credit pools per direction.
Track Posted, Non-Posted and Completion traffic with their header/data credit accounting for the selected virtual channel; one scalar TLP count is not a complete credit model.
Credit update uses DLLPs — not visible as TLPs.
Switch ports have independent credit pools per direction.