Part 4 · FSM & Control · Senior Prep

Full UART TX FSM (Verilog)

UART TX FSM: Full UART TX FSM (Verilog).

Full UART TX FSM (Verilog)

verilog

module uart_tx_fsm #(
  parameter int CLKS_PER_BIT = 87
) (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       tx_start_i,
  input  logic [7:0] tx_data_i,
  output logic       tx_busy_o,
  output logic       tx_done_o,
  output logic       tx_o
);
  typedef enum logic [2:0] {TX_IDLE, TX_START, TX_DATA, TX_STOP, TX_DONE} tx_state_t;
  tx_state_t state, state_n;

  logic [$clog2(CLKS_PER_BIT)-1:0] baud_cnt;
  logic [2:0] bit_idx;
  logic [7:0] shreg;
  logic baud_tick;

  assign baud_tick = (baud_cnt == CLKS_PER_BIT-1);

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state    <= TX_IDLE;
      baud_cnt <= '0;
      bit_idx  <= '0;
      shreg    <= '0;
    end else begin
      state <= state_n;

      if (state == TX_IDLE && tx_start_i) begin
        shreg <= tx_data_i;
      end

      if (state != TX_IDLE) begin
        if (baud_tick)
          baud_cnt <= '0;
        else
          baud_cnt <= baud_cnt + 1'b1;
      end else begin
        baud_cnt <= '0;
      end

      if (state == TX_DATA && baud_tick) begin
        shreg <= {1'b0, shreg[7:1]};
        bit_idx <= bit_idx + 3'd1;
      end else if (state == TX_IDLE) begin
        bit_idx <= '0;
      end
    end
  end

  always_comb begin
    state_n    = state;
    tx_o       = 1'b1; // line idles high
    tx_busy_o  = 1'b1;
    tx_done_o  = 1'b0;

    unique case (state)
      TX_IDLE: begin
        tx_busy_o = 1'b0;
        if (tx_start_i) state_n = TX_START;
      end
      TX_START: begin
        tx_o = 1'b0;
        if (baud_tick) state_n = TX_DATA;
      end
      TX_DATA: begin
        tx_o = shreg[0];
        if (baud_tick && bit_idx == 3'd7) state_n = TX_STOP;
      end
      TX_STOP: begin
        tx_o = 1'b1;
        if (baud_tick) state_n = TX_DONE;
      end
      TX_DONE: begin
        tx_done_o = 1'b1;
        state_n = TX_IDLE;
      end
      default: state_n = TX_IDLE;
    endcase
  end
endmodule

Deep dive

This lesson deepens Full UART TX FSM (Verilog) within fsm. Senior reviewers expect you to connect mechanism to controller/datapath, encoding, and multi-cycle protocols — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: illegal states handled, outputs defined every state. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

diagram

FULL UART TX FSM (VERILOG)

  inputs ──► [fsm] ──► mechanism ──► outputs
                │                │
           uart-tx     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

verilog

// bit counter + shift reg + baud tick

Step-by-step design procedure

Write the spec invariant (truth table, timing, or protocol rule).
Sketch block diagram — inputs, outputs, clock/reset domains.
Code the minimal correct version (no optimizations yet).
Run self-checking TB with corners: min, max, reset, idle.
Lint and review: width, latch, clock, CDC if applicable.
Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

diagram

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

Compare DUT vs reference on every stimulus vector
Capture first cycle of mismatch — not last
Log seed and plusargs for random regressions
Check reset release and clock alignment in TB
If waveform is ambiguous, add temporary assertions

Interview angle

Moore vs Mealy for timing-critical outputs?

diagram

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Full UART TX FSM (Verilog)": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Key takeaways

Connect Full UART TX FSM (Verilog) to controller/datapath, encoding, and multi-cycle protocols.
Spec → diagram → code → TB → lint is the default loop.
Document assumptions at block boundaries (width, signedness, latency).
Interview answers need mechanism + trade-off + example.

Common pitfalls

Skipping reference model — passes wrong together with DUT.
Optimizing before correct — ECO cost goes up 10×.
Ignoring tool warnings — lint/CDC/STA warnings are technical debt.
Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for Full UART TX FSM (Verilog) : UART TX baud error — measure bit period in TB vs spec.

Scenario resolution outline

Reproduce with minimal TB — one stimulus, one check.
Isolate failing cone (logic, FSM state, or bus beat).
Fix root cause — not symptom — in RTL or TB alignment.
Add regression test that fails without the fix.
Document invariant in comment or SVA for permanence.

Additional simulation pattern

verilog

// FSM state trace gold file
// cycle,state_q,outputs — compare each transition

Synthesis and sign-off notes

Elaborate clean — no OOM from unconstrained generate
Constraints cover all clocks and I/O delays
Cross-check RTL parameters vs integration top
Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Full UART TX FSM (Verilog)". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Extended design scenario

Scenario for Full UART TX FSM (Verilog) : UART TX baud error — measure bit period in TB vs spec.

Scenario resolution outline

Reproduce with minimal TB — one stimulus, one check.
Isolate failing cone (logic, FSM state, or bus beat).
Fix root cause — not symptom — in RTL or TB alignment.
Add regression test that fails without the fix.
Document invariant in comment or SVA for permanence.

Additional simulation pattern

verilog

// FSM state trace gold file
// cycle,state_q,outputs — compare each transition

Synthesis and sign-off notes

Elaborate clean — no OOM from unconstrained generate
Constraints cover all clocks and I/O delays
Cross-check RTL parameters vs integration top
Attach sim log + seed to code review

Lab exercise (45–60 min)

Extended theory

FSMs are the executable spec for control. If the FSM is wrong, no amount of datapath optimization fixes functionality; if the FSM is right but wide, encoding and output registration fix timing.

For "Full UART TX FSM (Verilog)", the invariant you defend in review is: behavior matches spec under all legal input sequences, reset flows, and backpressure patterns—not just the happy path shown in introductory diagrams.

Write the invariant as a comment above the module or as an SVA property when possible. Future you (and formal tools) will treat it as the contract.

Waveform reading guide

diagram

WAVEFORM NARRATIVE — Full UART TX FSM (Verilog)

cycle 0: reset asserted, outputs safe/idle
cycle 1-2: reset held, clocks running
cycle 3: reset released, first legal inputs
cycle 4+: check output latency (N cycles)
mark FIRST mismatch cycle — not last

Second worked example

Alternate pattern emphasizing debug, coverage, or integration:

verilog

// FSM coverage — visit every state
cover property (@(posedge clk) state == RUN);
cover property (@(posedge clk) state == ERROR);

Comparison: naive vs production

diagram

NAIVE APPROACH              PRODUCTION APPROACH
quick hack, one sim vector    self-checking TB + corners
ignore lint warnings          zero new waivers
implicit widths               explicit casts/parameters
undocumented latency          latency in module header comment

Additional interview questions

Explain Full UART TX FSM (Verilog) to a verification engineer — what would they assert?
What breaks first at high frequency or low voltage?
What is your rollback plan if synthesis QoR is unacceptable?
How would you debug this block with only a 32-bit GPIO trace?

Follow-up interview model answer

diagram

Q: What is the #1 mistake with Full UART TX FSM (Verilog)?
A:
  MECHANISM: [core rule in one line]
  MOTIVATION: why teams care in tape-out
  PITFALL: what juniors do wrong
  EXAMPLE: one Verilog line or one waveform event

Hands-on lab part 2

Fork the worked example; add one assertion or SVA cover.
Inject a bug deliberately; confirm TB or assertion catches it.
Write 5-bullet PR description for your change.
Peer review: can a teammate enable the block without asking you?

Sign-off evidence checklist

Directed sim log attached (PASS, seed noted)
Lint report clean for touched files
If sequential: reset + clocking section in README
If bus-facing: protocol cheat sheet in module doc
If timing-critical: note expected critical path endpoint

Practice this lesson

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Full UART TX FSM (Verilog)