8N1 means 8 data bits, no parity, 1 stop bit. With the start bit, each byte takes 10 bit-times.
Bit time | Line value | Purpose |
|---|---|---|
0 | 0 | Start bit: the falling edge tells the receiver a frame begins and gives it a time reference |
1 to 8 | D0 … D7 | Data, least significant bit first |
9 | 1 | Stop bit: returns the line to idle so the next start bit produces a falling edge |
There is no clock on the wire. The receiver finds the start edge and samples mid-bit, so both ends need closely matched baud rates.
Read the picture from left to right, one box per bit time. There is no clock lane because the wire carries none.
Start bit: the falling edge at the start of the shaded orange box is the only timing reference the receiver gets.
Data bits: 0xA5 is 1010 0101. The line shows D0 first, so the bits appear in the order 1, 0, 1, 0, 0, 1, 0, 1, which is the byte read from the right.
Stop bit: the shaded blue box returns the line to idle high, so the next start bit makes a falling edge.
System clock | Baud | f/baud | CLKS_PER_BIT | Period error e_T | Actual baud / baud error e_B |
|---|---|---|---|---|---|
12 MHz | 115200 | 104.166667 | 104 | −0.1600 % | 115384.615 / +0.160256 % |
25 MHz | 115200 | 217.013889 | 217 | −0.0064 % | 115207.373 / +0.0064004 % |
50 MHz | 115200 | 434.027778 | 434 | −0.0064 % | 115207.373 / +0.0064004 % |
100 MHz | 115200 | 868.055556 | 868 | −0.0064 % | 115207.373 / +0.0064004 % |
50 MHz | 9600 | 5208.333333 | 5208 | −0.0064 % | 9600.614 / +0.0064004 % |
Negative period error means shorter bits and positive baud error. Values use the unrounded clock/baud ratio. Receiver tolerance depends on start detection, oversampling, frame length and stop sampling; half-bit drift is only an idealized upper bound.
Illustrative allocation: reserve 2% relative baud mismatch, with 0.5% oscillator error at each endpoint and up to 0.2% divider error at each endpoint. The conservative sum is 1.4%, leaving 0.6% of this allocation. Compare the actual ratio B_TX/B_RX - 1 at opposite oscillator corners; equal signed divider errors can cancel. This allocation is not a receiver guarantee: select and check the receiver's specified mode and frame size, for example Microchip's asynchronous operational range.
One bit = 868 clocks × 10 ns = 8.68 µs. A 10-bit frame takes 86.8 µs.