0x96 is 1001 0110. Sent least significant bit first, the line carries 0, 1, 1, 0, 1, 0, 0, 1. MSB-first would send 1, 0, 0, 1, 0, 1, 1, 0, so this byte shows the order on the line. (A byte such as 0xA5, 1010 0101, reads the same in both directions and would hide an order bug.) CTS permission is tied high throughout this waveform.
The table labels each bit time against the waveform above.
Cycles | State | Line (tx) | Bit |
|---|---|---|---|
0 to 1 | IDLE | 1 | idle, |
2 to 5 | START | 0 | start bit |
6 to 9 | DATA | 0 | D0 = 0 |
10 to 13 | DATA | 1 | D1 = 1 |
14 to 17 | DATA | 1 | D2 = 1 |
18 to 21 | DATA | 0 | D3 = 0 |
22 to 25 | DATA | 1 | D4 = 1 |
26 to 29 | DATA | 0 | D5 = 0 |
30 to 33 | DATA | 0 | D6 = 0 |
34 to 37 | DATA | 1 | D7 = 1 |
38 to 41 | STOP | 1 | stop bit; |
42 on | IDLE | 1 | back to idle |
The start bit and D0 are both 0, so the line stays low for 8 clocks (cycles 2 to 9); D5 and D6 do the same in cycles 26 to 33. A receiver must count bit times rather than watch for edges.
The first data bit time (cycles 6 to 9) is low because D0, the least significant bit of 0x96, is 0. An MSB-first transmitter would drive D7 = 1 there. The testbench offers 0x96 as a directed byte, so an MSB-first mutant fails on it.
D7 = 1 runs into the stop bit, so the line stays high from cycle 34 through the stop bit and idle.
State changes land on bit boundaries. Inside DATA the bit position is held by bit_idx, not by the state.
The frame runs from cycle 2 to cycle 41: 40 clocks, or 10 bits at 4 clocks each.
tx_ready go high in cycle 41 and not in cycle 42 when the state becomes IDLE?Because tx_ready includes the condition state == STOP && tick. In the last clock of the stop bit the transmitter is already able to accept a new byte, so the next start bit can follow immediately.