One-stage stream pipeline register

One-stage stream pipeline register

module axis_pipe #(
  parameter int DW = 64,
  parameter int KW = DW/8
) (
  input  logic          clk,
  input  logic          rst_n,
  input  logic          s_tvalid,
  output logic          s_tready,
  input  logic [DW-1:0] s_tdata,
  input  logic [KW-1:0] s_tkeep,
  input  logic          s_tlast,
  output logic          m_tvalid,
  input  logic          m_tready,
  output logic [DW-1:0] m_tdata,
  output logic [KW-1:0] m_tkeep,
  output logic          m_tlast
);
  logic full;
  logic [DW-1:0] data_q;
  logic [KW-1:0] keep_q;
  logic          last_q;

  wire push = s_tvalid && s_tready;
  wire pop  = m_tvalid && m_tready;

  assign s_tready = !full || pop;
  assign m_tvalid = full;
  assign m_tdata  = data_q;
  assign m_tkeep  = keep_q;
  assign m_tlast  = last_q;

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      full   <= 1'b0;
      data_q <= '0;
      keep_q <= '0;
      last_q <= 1'b0;
    end else begin
      if (push) begin
        data_q <= s_tdata;
        keep_q <= s_tkeep;
        last_q <= s_tlast;
        full   <= 1'b1;
      end else if (pop) begin
        full <= 1'b0;
      end
    end
  end
endmodule

This stage enforces stable output payload during backpressure while keeping one-beat throughput when downstream is ready.

Deep dive

This lesson deepens One-stage stream pipeline register within memory-buses. Senior reviewers expect you to connect mechanism to memory inference, valid/ready, and AXI family protocols — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: protocol assertions, backpressure tested. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

ONE-STAGE STREAM PIPELINE REGISTER

  inputs ──► [memory-buses] ──► mechanism ──► outputs
                │                │
           axi-stream     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// tvalid/tready/tdata handshake

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Skid buffer vs FIFO on valid/ready?

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "One-stage stream pipeline register": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Key takeaways

• Connect One-stage stream pipeline register to memory inference, valid/ready, and AXI family protocols.

• Spec → diagram → code → TB → lint is the default loop.

• Document assumptions at block boundaries (width, signedness, latency).

• Interview answers need mechanism + trade-off + example.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for One-stage stream pipeline register : SRAM read returns old data — align read latency in TB (+1 cycle).

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// AXI beat checker
assert (valid && ready) |-> stable_data;

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "One-stage stream pipeline register". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.

Extended design scenario

Scenario for One-stage stream pipeline register : SRAM read returns old data — align read latency in TB (+1 cycle).

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// AXI beat checker
assert (valid && ready) |-> stable_data;

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "One-stage stream pipeline register". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.

Extended theory

Memory and bus interfaces are integration surfaces: software, DV, and PD all touch the same valid/ready or AXI signals—document beat-level behavior explicitly.

For "One-stage stream pipeline register", the invariant you defend in review is: behavior matches spec under all legal input sequences, reset flows, and backpressure patterns—not just the happy path shown in introductory diagrams.

Write the invariant as a comment above the module or as an SVA property when possible. Future you (and formal tools) will treat it as the contract.

Waveform reading guide

WAVEFORM NARRATIVE — One-stage stream pipeline register

cycle 0: reset asserted, outputs safe/idle
cycle 1-2: reset held, clocks running
cycle 3: reset released, first legal inputs
cycle 4+: check output latency (N cycles)
mark FIRST mismatch cycle — not last

Second worked example

Alternate pattern emphasizing debug, coverage, or integration:

// AXI beat monitor
always @(posedge clk)
  if (valid && ready) beat_cnt++;

Comparison: naive vs production

NAIVE APPROACH              PRODUCTION APPROACH
quick hack, one sim vector    self-checking TB + corners
ignore lint warnings          zero new waivers
implicit widths               explicit casts/parameters
undocumented latency          latency in module header comment

Additional interview questions

• Explain One-stage stream pipeline register to a verification engineer — what would they assert?

• What breaks first at high frequency or low voltage?

• What is your rollback plan if synthesis QoR is unacceptable?

• How would you debug this block with only a 32-bit GPIO trace?

Follow-up interview model answer

Q: What is the #1 mistake with One-stage stream pipeline register?
A:
  MECHANISM: [core rule in one line]
  MOTIVATION: why teams care in tape-out
  PITFALL: what juniors do wrong
  EXAMPLE: one Verilog line or one waveform event

Hands-on lab part 2

1. Fork the worked example; add one assertion or SVA cover.

2. Inject a bug deliberately; confirm TB or assertion catches it.

3. Write 5-bullet PR description for your change.

4. Peer review: can a teammate enable the block without asking you?

Sign-off evidence checklist

• Directed sim log attached (PASS, seed noted)

• Lint report clean for touched files

• If sequential: reset + clocking section in README

• If bus-facing: protocol cheat sheet in module doc

• If timing-critical: note expected critical path endpoint