No at I/O boundaries if legal; internal state timing changes. Illegal retime across feedback without enough delay causes functional change.
SAMPLE Q&A
┌─────────┐ ┌──────────────┐ ┌─────────┐
│ inputs │ ──► │ sequential │ ──► │ outputs │
└─────────┘ │ mechanism │ └─────────┘
└──────────────┘
│
pitfalls / when-to-use
(sample-qanda)Pipelining adds a spec-visible stage; retiming moves existing registers. Pipelining increases throughput by design; retiming optimizes an existing structure.
This lesson deepens Sample Q&A within sequential. Senior reviewers expect you to connect mechanism to register templates, pipelines, and flow control — not just define terms.
Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.
At tape-out quality, every block needs a sign-off story: reset complete, NBA in flops, pipeline latency documented. Treat this lesson as building one paragraph of that story for your project documentation.
SAMPLE Q&A
inputs ──► [sequential] ──► mechanism ──► outputs
│ │
retiming verify in sim + lintSynthesizable pattern for this topic — simulate locally and compare against your reference.
// move logic across register boundary for timingWrite the spec invariant (truth table, timing, or protocol rule).
Sketch block diagram — inputs, outputs, clock/reset domains.
Code the minimal correct version (no optimizations yet).
Run self-checking TB with corners: min, max, reset, idle.
Lint and review: width, latch, clock, CDC if applicable.
Iterate for timing/area only after functionally proven.
METRIC TYPICAL LEVER
Logic levels algebra / pipelining
Register count retiming / sharing
Wire fanout duplication / pipeline
Power clock gating / operand isolation
Debug visibility status flags / SVA / waveform probesCompare DUT vs reference on every stimulus vector
Capture first cycle of mismatch — not last
Log seed and plusargs for random regressions
Check reset release and clock alignment in TB
If waveform is ambiguous, add temporary assertions
Pipeline stall vs bubble — when each?
MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenarioExtend the worked example for "Sample Q&A": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.
Connect Sample Q&A to register templates, pipelines, and flow control.
Spec → diagram → code → TB → lint is the default loop.
Document assumptions at block boundaries (width, signedness, latency).
Interview answers need mechanism + trade-off + example.
Skipping reference model — passes wrong together with DUT.
Optimizing before correct — ECO cost goes up 10×.
Ignoring tool warnings — lint/CDC/STA warnings are technical debt.
Undocumented clock/reset domain — integration surprises.
Scenario for Sample Q&A: Pipeline shows wrong result — align TB sample point with end of pipe.
Reproduce with minimal TB — one stimulus, one check.
Isolate failing cone (logic, FSM state, or bus beat).
Fix root cause — not symptom — in RTL or TB alignment.
Add regression test that fails without the fix.
Document invariant in comment or SVA for permanence.
// Pipeline latency check
repeat (PIPE_LAT) @(posedge clk);
check_exp(dut_out);Elaborate clean — no OOM from unconstrained generate
Constraints cover all clocks and I/O delays
Cross-check RTL parameters vs integration top
Attach sim log + seed to code review
Implement or extend the worked example for "Sample Q&A". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.
Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.Sequential logic is where protocols live: latency, handshake, reset sequencing, and pipeline bubbles are all register-scheduling problems—not RTL syntax problems.
For "Sample Q&A", the invariant you defend in review is: behavior matches spec under all legal input sequences, reset flows, and backpressure patterns—not just the happy path shown in introductory diagrams.
Write the invariant as a comment above the module or as an SVA property when possible. Future you (and formal tools) will treat it as the contract.
WAVEFORM NARRATIVE — Sample Q&A
cycle 0: reset asserted, outputs safe/idle
cycle 1-2: reset held, clocks running
cycle 3: reset released, first legal inputs
cycle 4+: check output latency (N cycles)
mark FIRST mismatch cycle — not lastAlternate pattern emphasizing debug, coverage, or integration:
// Clock-domain marker in TB
always @(posedge clk) begin
if (valid) $strobe("t=%0t data=%h", $time, data);
endNAIVE APPROACH PRODUCTION APPROACH
quick hack, one sim vector self-checking TB + corners
ignore lint warnings zero new waivers
implicit widths explicit casts/parameters
undocumented latency latency in module header commentExplain Sample Q&A to a verification engineer — what would they assert?
What breaks first at high frequency or low voltage?
What is your rollback plan if synthesis QoR is unacceptable?
How would you debug this block with only a 32-bit GPIO trace?
Q: What is the #1 mistake with Sample Q&A?
A:
MECHANISM: [core rule in one line]
MOTIVATION: why teams care in tape-out
PITFALL: what juniors do wrong
EXAMPLE: one Verilog line or one waveform eventFork the worked example; add one assertion or SVA cover.
Inject a bug deliberately; confirm TB or assertion catches it.
Write 5-bullet PR description for your change.
Peer review: can a teammate enable the block without asking you?
Directed sim log attached (PASS, seed noted)
Lint report clean for touched files
If sequential: reset + clocking section in README
If bus-facing: protocol cheat sheet in module doc
If timing-critical: note expected critical path endpoint