NanoSoC is non-coherent: one core with an instruction cache, no data cache, and a DMA path that software keeps consistent by placement and discipline. The moment a second core or a caching master arrives, the interconnect gains a second job: every cacheable read and write must find or invalidate every other copy. This topic teaches that job at integration level only, with illustrative numbers built from the NanoSoC line size (16 bytes), line fill (125 ns) and job size (64 words); the protocol itself belongs to the cache-coherency course.
Lesson | After it you can... |
|---|---|
Name the snoop traffic, count it for a NanoSoC job, and compare broadcast with a directory. | |
Cost software maintenance against an I/O-coherent port for a 64-word job. | |
List what adding one coherent master costs the NanoSoC fabric, with a snoop budget row. |
Suggested order: top to bottom. The general change first, the DMA option that matters most to integrators, then the concrete NanoSoC delta. For the protocol see the coherency course; for the DMA software side see the I/O-coherency lessons linked from the second lesson.
Because the integrator decides which masters are coherent, where snoop traffic flows, and what it costs in bandwidth and area. The protocol course teaches how coherence works; this topic teaches what it costs the chip.