SRAM1 and the reset controller are secure-only on NanoSoC, and the enforcement is not a comment in the map: an AxPROT filter in the interconnect and a per-slot check in the APB decoder return SLVERR to any non-secure access. That is all NanoSoC builds. It has no master-ID table: policies such as the SBR must never touch the reset controller are a proposed extension, treated as such in the second lesson. This topic places the filters, rehearses the failures that follow when a bridge drops the sideband or a filter is misprogrammed, and states the known gap in the partition. The security architecture around the filters belongs to the memories and security section; this topic owns the fabric enforcement.
Lesson | After it you can... |
|---|---|
Place AxPROT filters per region, predict the response for each security state and complete a denied burst without hanging the requester. | |
Write a complete per-region policy table and compare what NanoSoC enforces with a proposed master-ID firewall. | |
Distinguish secure faults from decode errors and debug a wrongly denied master. |
Suggested order: top to bottom. Filters first, policy tables second, failure drill third. For the attribute theory see Access Attributes; for firewall placement theory see Firewalls and Filtering.
The interconnect secure filter answered. The address did decode to a slave region, so DECERR (no slave claimed it) would be false: the region exists and refused the access, which is SLVERR. Hiding the layout would be a policy choice NanoSoC does not make.