The protocol course teaches what AXI means; this topic teaches what the integrator must get right so that it keeps meaning it after two masters, a clock crossing and a bridge. The jobs are concrete: size the ID fields so responses return to the right master, split every burst that would cross a 4 KB page, and cross the 192 to 96 MHz boundary without losing a beat. Each lesson states the rule, works it on NanoSoC numbers, and gives the check that catches the violation.
Lesson | After it you can... |
|---|---|
Size ID widths through the fabric and explain why AXI4 write data has no ID. | |
Split any burst at 4 KB boundaries and verify the split in simulation. | |
Cross the CPU to fabric boundary and justify why NanoSoC converts clocks but not widths. |
Suggested order: top to bottom. IDs first, because every later lesson assumes responses find their master; then the 4 KB rule, which is the commonest protocol violation a burst-issuing master commits; then conversion, which is where the CDC discipline enters. For signal-level protocol meaning see AXI4 and for width theory Width and Endianness Conversion.
The master-index field of the fabric ID grows from one bit to two (three masters), the outstanding-transaction budget per slave must cover two CPUs plus the SBR, and the round-robin arbitration table gains a master. The 4 KB rule and the bridge timings do not change.