Sooner or later someone proposes a network-on-chip for every design, including ones with two masters. This topic keeps the integration view only: when a NoC replaces a crossbar, how its address-to-node table must match the chip map, how AXI IDs and message classes cross its network interfaces, and what its clock and power islands do to the integrator's checklist. The theory of topologies, routing, credit flow control and virtual channels is taught once, in the architecture course, and linked from each lesson; it is not repeated here.
Lesson | After it you can... |
|---|---|
Price the packet overhead of a NoC against a crossbar, header included, and name the crossover. | |
State what the integrator must configure and check: virtual networks per message class, and credit sizing in flits. | |
Check the address-to-node table against the chip map, handle IDs at the network interface, and review a NoC's clock and power crossings. | |
Show with numbers that a NoC loses on NanoSoC, and name the growth that would change the answer. |
Suggested order: top to bottom. Crossover first, the little router theory the integrator needs second, the integration checks third, verdict on NanoSoC last. For topology maths see On-Chip Networks; for the QoS and deadlock theory reused here see Quality of Service and Deadlock and Liveness.
What wire or scaling problem does the crossbar have here: the NoC is an answer to long wires and many masters, and with three masters there is no such problem to solve.