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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
    • Topologies and Bridges
    • AXI Integration Details
    • Ordering and Deadlock at the Top
    • QoS and Arbitration
    • NoC Basics
      • Packets Versus Crossbar
      • Routers, Virtual Channels and Flow Control
      • The NoC as an Integration Task
      • Does NanoSoC Need a NoC
    • Coherent Interconnect View
    • Firewalls and Protection
    • Bandwidth and Latency Verification
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←NoC Basics
  1. Topics
  2. SoC Design
  3. Interconnect and Bus Fabrics
  4. NoC Basics
  5. Does NanoSoC Need a NoC
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    Part 4 of 14, lesson 17 of 26Part 4 of 14/Interconnect and Bus Fabrics/Lesson 17 of 26All levels

    Does NanoSoC Need a NoC

    Running the numbers: two masters, four slaves, one small die, and a verdict with a revisit clause.

    Why it matters

    Every fabric decision needs a worked no: the option considered, the numbers that reject it, and the growth that would reopen it. Without the written no, the NoC returns in every planning meeting. This lesson writes it once for NanoSoC, in a form that ports to any small chip.

    The core idea

    NanoSoC has two masters and four slaves on one small die: crossbar wiring is 2 x 4 = 8 master-to-slave paths, every path closes timing at 96 MHz, and the hop count a NoC would add exceeds the whole crossbar traversal it replaces. The script below prices the fabric-only portion of a CPU word from SRAM both ways: the crossbar spends two system clocks on address plus data, while a two-hop NoC (HOPS = 2 is an illustrative choice) spends six router-pipeline cycles plus serialisation. In whole-access terms the CPU's 93.75 ns SRAM word becomes about 145.8 ns, 55.6 percent slower, for no gain in bandwidth. The verdict is crossbar, with a revisit clause (a teaching guideline, not a law): past roughly eight masters, 96 paths for an eight-master twelve-slave chip against 8 today, or when a second clock and power island multiplies the bridge count, the wiring and isolation arithmetic gets redone.

    example.py
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    # NanoSoC teaching values: fabric-only path for one CPU word from SRAM.
    T_SYS_NS = 10.4167
    XBAR_FABRIC_NS = 2 * T_SYS_NS # address + data through the crossbar
    HOPS = 2 # illustrative
    PIPE = 3 # illustrative router pipeline cycles per hop
    NOC_FABRIC_NS = (HOPS * PIPE + 1) * T_SYS_NS # pipeline + 4-byte serialisation
    assert abs(XBAR_FABRIC_NS - 20.8) < 0.1
    assert abs(NOC_FABRIC_NS - 72.9) < 0.5
    assert NOC_FABRIC_NS > 3 * XBAR_FABRIC_NS # 3.5x the fabric latency
    # whole access: swap the fabric part inside the 93.75 ns CPU word
    whole_noc = 93.75 - XBAR_FABRIC_NS + NOC_FABRIC_NS
    assert abs(whole_noc - 145.8) < 0.1
    assert abs(whole_noc / 93.75 - 1 - 0.556) < 0.001 # +55.6 percent
    # wiring: master-to-slave paths of a crossbar
    assert 2 * 4 == 8 and 8 * 12 == 96
    print("PASS: NoC fabric path 72.9 ns vs crossbar 20.8 ns, CPU word 93.75 -> 145.8 ns, no win at 2x4")

    What the review looks for

    • The rejected option is priced, not dismissed: cycles, whole-access latency and wiring paths side by side.

    • The revisit clause names numbers, not feelings: master count and island count that reopen the choice, marked as guidelines.

    • No generator, licence or team ramp-up is spent before the crossover is shown.

    Verify and debug

    Recheck the verdict whenever the master count or the floorplan changes: add the new masters to the wiring estimate and the new islands to the bridge count, and rerun the hop arithmetic. The failure to watch for is success: a third master and a fourth slave still favour the crossbar, and only the numbers say when that stops being true.

    Paying NoC overheads without NoC problems: router area and hop latency on a fabric small enough that a crossbar closes timing trivially. The guard is the written no with its revisit numbers, reviewed whenever the block list grows.

    If asked to defend no-NoC, give the three numbers: master count, worst hop penalty (+55.6 percent on a CPU word) and wiring paths (8). Then state the revisit clause unprompted: that is what turns a preference into an engineering decision.

    Check yourself NanoSoC gains six more masters and a second power island. What is re-examined first?

    The wiring and bridge arithmetic: eight masters times the slave count in crossbar paths, plus the new island's crossings. If the hop penalty beats that cost, the NoC clause triggers.

    Related topics

    • The NoC as an Integration Task

    • Architecture: Topology Families Compared

    • Next: Coherent Interconnect View

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    See also

    • Packets Versus Crossbar
    • Routers, Virtual Channels and Flow Control