A crossbar connects every master to every slave with dedicated paths and a multiplexer per slave: the wiring grows with masters times slaves and every path must close timing across the whole die. For a handful of masters up to about eight (a teaching guideline, which depends on die size and technology) that is the cheapest correct answer. Past that, or across a large die where wire delay dominates, one shared packet link between routers beats a full mesh of wide buses. The packet makes sharing possible: address, control and data wrapped with a destination, routed hop by hop instead of switched end to end.
A NoC replaces the central switch with routers joined by links. A network interface packetises each transaction, routers forward by destination, and every packet pays a header flit, a router pipeline delay per hop and serialisation on the link. The topology maths, routing algorithms and flow control belong to the architecture course (topology families, latency and bandwidth maths); the integrator needs only the price, shown below.
# Illustrative values: where packet overhead stops mattering.
# A hop costs H cycles of router pipeline; the link moves one 4-byte flit per cycle;
# every packet carries one header flit.
H = 3 # illustrative router pipeline depth in cycles
WIDTH = 4 # link bytes per cycle
HDR = 1 # header flits per packet
def noc_cycles(hops, payload_bytes, header_flits=HDR):
return hops * H + payload_bytes / WIDTH + header_flits
reg = noc_cycles(2, 4) # 4-byte register read across 2 hops
burst = noc_cycles(2, 64) # 64-byte burst across 2 hops
assert reg == 8.0 and burst == 23.0
overhead_reg = (reg - 1) / reg # everything except the one data flit
overhead_burst = (burst - 16) / burst # everything except the 16 data flits
assert abs(overhead_reg - 0.875) < 1e-9 # short traffic is almost all overhead
assert abs(overhead_burst - 0.304) < 0.001 # hops 6 + header 1 = 7 of 23 cycles
# without the header flit the burst would be 22 cycles and 27.3 percent
assert noc_cycles(2, 64, header_flits=0) == 22.0
# crossbar wiring: master-to-slave paths grow as M x S
assert 2 * 4 == 8 and 8 * 12 == 96
print("PASS: register read 8 cycles (87.5 percent overhead), 64-byte burst 23 cycles (30.4 percent)")The fabric choice names the crossover it assumes (master count and die span) and marks it as a guideline, not a law.
Short-access latency is budgeted with hop count and header included, never with zero-hop optimism.
Burst traffic is shown to amortise the header and pipeline overhead that short traffic pays in full.
Check the NoC decision with the latency arithmetic above before any generator is configured: if single-hop crossbar latency already meets every deadline, the NoC is complexity without a customer. Where a NoC is chosen, compare the generator's reported latency for a register read and a 64-byte burst with the two numbers here; a large gap means a longer pipeline or an extra hop that was not budgeted.
Eight cycles: six of router pipeline, one header flit and one data flit. Short traffic pays almost pure overhead, which is why registers stay on local buses.