Two failures share one root: an interrupt that arrives before the data it announces, and a fabric that freezes under one specific traffic mix and never recovers. Both are integration properties, invisible inside any single block. This topic states the ordering the integrator owes software, shows how dependency cycles through bridges and shared slaves stop the chip, and gives the prevention and debug method. The protocol theory behind it is linked, not repeated.
Lesson | After it you can... |
|---|---|
State the ordering guarantees across the NanoSoC bridges and place the point of serialisation. | |
Draw the dependency cycle behind a bridge hang and name the shared resource. | |
Apply channel-dependency rules and debug a frozen fabric to its cycle. |
Suggested order: top to bottom. Ordering first, because a deadlock-free fabric that reorders wrongly still corrupts; then the deadlock mechanism, then the proof and the debug method. For the protocol rules underneath see Ordering Across Bridges and for the theory Deadlock and Liveness.
Either, and the distinction decides the debug: an ordering bug completes with wrong results, a deadlock stops completing at all. Check for forward progress first; if beats still move, it is ordering.