Every byte the CPU fetches and every word the DMA moves crosses the same piece of hardware: a 2-master by 4-slave crossbar clocked at 96 MHz, with a bridge down to a slow peripheral bus hanging off one of its ports. This topic explains why that shape was chosen, how the bridge in the middle really behaves cycle by cycle, and what each crossing costs in latency and area. The numbers are the NanoSoC link and latency tables; the bridge timing matches the DMA's 3-clock APB access.
Lesson | After it you can... |
|---|---|
Choose between a shared bus and a crossbar for a given master count, and place the APB tree. | |
Trace a write and a read through the axi2apb bridge and the apb_cdc, wait states included. | |
Budget the latency and area of each NanoSoC bridge and say what hangs if one is gated or reset wrongly. | |
Place a register slice on a fabric path, price its latency and avoid the half-throughput slice. |
Suggested order: top to bottom. The first lesson picks the topology, the second opens the bridge that the topology depends on, the third prices every crossing, and the fourth adds the pipeline stage you reach for when a path misses timing. The AXI detail behind the first two lessons lives in the next topic, AXI Integration Details.
The UART needs a few bytes per millisecond, not hundreds of megabytes per second. Hanging it off the APB tree keeps the fast fabric narrow and lets the slow segment run at 24 MHz in the always-on domain; the price is about 281 ns per access, which a UART never notices.