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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
    • Designing the Address Map
    • Implementing Address Decode
    • Decode Errors and Default Slaves
    • Register Maps and Banks
    • Security and Privilege Regions
    • The Software View and the Hardware-Software Contract
      • Generated Headers and the Map Document
      • Endianness, Access Width and Ordering
      • Errata and Software Workarounds
    • IP-XACT and Automated Assembly
    • Memory-Map Verification
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←The Software View and the Hardware-Software Contract
  1. Topics
  2. SoC Design
  3. Memory Maps and Address Decode
  4. The Software View and the Hardware-Software Contract
  5. Errata and Software Workarounds
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    Part 3 of 14, lesson 20 of 26Part 3 of 14/Memory Maps and Address Decode/Lesson 20 of 26All levels

    Errata and Software Workarounds

    How a hardware bug becomes a numbered erratum with a recorded workaround, using the NanoSoC contract traps.

    Why it matters

    Silicon comes back with bugs. The difference between a respin and a shipped product is often a software workaround, and the difference between a workaround and folklore is whether it is written down where driver authors will find it, against the map version it applies to. Errata handling is part of the hardware-software contract; this lesson defines the smallest honest process.

    The core idea

    An erratum entry has six fields: an identifier, the symptom as software observes it, the root cause in hardware terms, the silicon revisions affected, the workaround stated as a driver rule, and the verification that proves the workaround. The lifecycle matters as much as the fields: an entry is opened when a bug is confirmed, the workaround is reviewed like code, the entry is closed only when fixed silicon is verified or the workaround becomes permanent documentation. Workarounds are recorded against the map and register specification versions, because a workaround for one revision applied blindly to another is how fixed hardware acquires phantom restrictions.

    Three of NanoSoC's documented DMA behaviours are usage restrictions, recorded in the table below. A fourth entry shows the genuine erratum shape for contrast: a true silicon deviation, the 8 KB decode window found in the verification topic, where an early revision's DMA select covered two slots. Note the difference in kind: restrictions describe hardware working as specified but surprising every driver, while an erratum describes hardware deviating from its specification, and only the erratum can be closed by a silicon fix. The DMA's silent-write behaviour becomes: symptom, a reprogrammed job runs with stale LEN or KEY and no error; cause, writes ignored while BUSY by design; workaround, poll BUSY to zero before touching LEN or KEY. The sticky-ERR behaviour becomes: symptom, the interrupt never drops after a failed job followed by a good one; cause, GO clears DONE but not ERR; workaround, clear both bits by writing 0x6 to STATUS after every job. The CTRL behaviour becomes: symptom, the completion interrupt never arrives; cause, every CTRL write stores bit 1 into IRQ_EN, so writing 0x1 disarms it; workaround, always write 0x3 to start with the interrupt enabled. Note that all three are specified behaviours rather than silicon defects; the recording discipline treats them identically, because from the driver's seat a surprising specification and a bug feel exactly the same.

    Usage restrictions and known traps (hardware working as specified):

    Entry

    Symptom

    Driver rule (workaround)

    NSC-001 busy-ignored writes

    New LEN or KEY has no effect, no error

    Wait for BUSY = 0 before writing LEN or KEY

    NSC-002 sticky ERR

    Interrupt stuck after a failed then good job

    Write 0x6 to STATUS after every job

    NSC-003 CTRL stores IRQ_EN

    No completion interrupt after starting

    Write 0x3 to CTRL (IRQ_EN set) to start

    A genuine erratum, by contrast, deviates from the specification. Illustrative example in the same format: ERR-104, 8 KB DMA decode window, revisions A only. Symptom: after any SBR CTRL write, DMA output data has bit 0 flipped with COUNT correct. Cause: the DMA slot select covered slots 0 and 1, so the SBR write also wrote DMA KEY with value 1. Workaround: none safe in software on revision A; avoid combined SBR and DMA use, fixed in revision B by decoding addr[15:12]. Verification: the cross-talk regression test of the verification topic fails on revision A samples and passes on revision B. Only this kind of entry closes with a silicon fix; the three restrictions above are permanent documentation.

    What the review looks for

    • Every confirmed hardware bug has an entry with all six fields before the next software release, not after it.

    • Workarounds are stated as testable driver rules and linked from the register documentation the driver author reads.

    • Entries name affected revisions and the map version; a workaround that outlives its silicon is reviewed, not inherited silently.

    Verify and debug

    Each workaround gets a test that fails without it: start a job with CTRL written as 0x1 and watch the interrupt never fire, then apply the rule and watch it arrive. A workaround without such a test decays into superstition within two releases. Keep the errata list versioned with the map, so a software build can state exactly which entries it implements.

    A workaround passed by word of mouth and applied to the wrong revision or the wrong block: it masks the real symptom and wastes the debug session. If it is not in the errata list against a revision, it does not exist.

    If asked how you handle a silicon bug that software can dodge, describe the entry: symptom, cause, revisions, rule, proof. Then give one of the three NanoSoC rules as a worked example, including the test that fails without it.

    Check yourself Why are the three DMA entries recorded at all if the hardware behaves as specified?

    Because the contract is what software experiences, not what the specification intended. A behaviour that reliably surprises every driver author belongs in the recorded list with a rule. They are filed as usage restrictions rather than errata, because only a deviation from the specification is an erratum and only an erratum can close with a silicon fix.

    Related topics

    • Endianness, Access Width and Ordering

    • Memory-Map Verification

    • Verification First Principles: Errata and Workarounds

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    See also

    • Generated Headers and the Map Document