A wrong address must fail loudly and fast: an error response the CPU can trap, never a silence the CPU waits on forever. NanoSoC has three ways to say no, each from a different responder, and a default slave behind each decoder so that no address goes unanswered. This topic teaches the three responses as a diagnosis table, shows how to build a default slave that completes every burst correctly, and walks a debugging method through two decode bugs that were planted in this very map. For the protocol-level meaning of error responses see Unmapped addresses, decode errors and SLVERR; for the generic error-response theory see Error Responses.
Lesson | After it you can... |
|---|---|
Predict the exact response for any NanoSoC address and say which block sends it. | |
Build the DECERR and SLVERR responders and the APB default that answer every beat and never hang. | |
Localise a decode bug to its level with readback and bisection, and write the check that catches it. |
Suggested order: top to bottom. Learn the response table first, because the default-slave lesson implements two rows of it and the debugging lesson reads the third kind of symptom off it. Every address in the table is a NanoSoC teaching value from the design specification.
SLVERR from the interconnect's secure filter: SRAM1 is secure-only, so a non-secure access is denied at the first level. The address is mapped, which is why the answer is SLVERR and not DECERR.