Everything in this section so far is a claim; this topic is where the claims are tested. Map verification is deliberately unglamorous: sweep every region and every hole, read every register back at reset, exercise every access type, probe the aliases in a controlled test mode, and then freeze the four planted bugs into regression tests so they can never come back. NanoSoC is the ideal size for it, the whole matrix fits in a few dozen directed accesses. The general strategy of what to verify where lives in the verification courses; here the scope is the map, tested the way a chip team actually signs one off. See also Security Verification for the strategy this topic executes.
Lesson | After it you can... |
|---|---|
Predict every probe answer from the map and check reset values and access types. | |
Prove the alias is the only alias and every select reaches a responder. | |
Turn four named bugs into permanent regression tests with sign-off criteria. |
Suggested order: top to bottom. Sweeps establish the expected answers, probing hunts for the unexpected ones, and the planted bugs convert surprises into permanent guards.
Because the failures live between blocks: a wrong base in the decode, a miswired address bit, a responder nobody instantiated. Block tests cannot see a wiring error by construction; only an addressed access from a master can.