Two regions on NanoSoC refuse the wrong visitor: SRAM1 and the reset-and-power controller admit secure accesses only. Everything else about that refusal is integration detail: which signal carries the caller's state, which block checks it, what answers when it fails, and how the stream bridge's own security bit can route a whole DMA copy into a wall. This topic teaches the memory-map side of that story: the attributes, the two filter placements, the access-control table and its tests. The full chip security architecture, root of trust, lifecycle states and debug lockout, is covered later in the Memories, Boot and Security section; here the scope is deliberately the map and nothing more. For the attribute theory see Access Attributes and Firewalls and Filtering.
Lesson | After it you can... |
|---|---|
Read the security column of the map and state what each master may touch. | |
Place both NanoSoC checks and walk the SBR non-secure reset bug end to end. | |
Generate the full master-by-region test matrix and prove it complete with a script. |
Suggested order: top to bottom. Attributes first, then placement, then evidence. Readers chasing one specific SLVERR can start at lesson two and follow the links back.
The access is refused with SLVERR at the slot decoder. The correct route is secure software reading RST_CAUSE on the driver's behalf; the register is secure-only because the block it lives in can reset the chip and control its power.