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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
    • Designing the Address Map
      • What an Address Map Is
      • Sizes, Alignment and Power-of-Two Windows
      • Holes, Aliases and Reserved Space
      • Planning for Growth and Banks
    • Implementing Address Decode
    • Decode Errors and Default Slaves
    • Register Maps and Banks
    • Security and Privilege Regions
    • The Software View and the Hardware-Software Contract
    • IP-XACT and Automated Assembly
    • Memory-Map Verification
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Memory Maps and Address Decode
  1. Topics
  2. SoC Design
  3. Memory Maps and Address Decode
  4. Designing the Address Map

Part 3 of 14Part 3 of 14/Memory Maps and Address DecodeAll levels

Designing the Address Map

Regions, attributes, alignment, holes, aliases and growth planning, all on the NanoSoC map.

  • 4topics
  • 4lessons

The address map is the first document an integrator writes and the last one anyone is allowed to change casually. This topic builds it from scratch on NanoSoC: what a region promises, why every window is a power of two sitting on a multiple of its own size, what lives in the holes between regions, why the DMA appears sixteen times, and how to leave room for the next peripheral without moving anything. Every number comes from the NanoSoC design specification.

Lesson

After it you can...

What an Address Map Is

Read the NanoSoC map as a contract and name every region attribute.

Sizes, Alignment and Power-of-Two Windows

Justify each base and size, and run the alignment and overlap checker.

Holes, Aliases and Reserved Space

Say what answers in each hole and why software must never probe one.

Planning for Growth and Banks

Place a second DMA and a bigger SRAM without moving any existing region.

Suggested order: top to bottom. The first lesson reads the map, the second checks its arithmetic, the third walks the empty spaces, and the fourth grows it. The decode topic next door (Implementing Address Decode) turns this map into gates.

Check yourself A new peripheral needs 3 KB of registers. How large is its map window and why?

4 KB: windows are powers of two, so 3 KB rounds up to 4 KB, and the base must be a multiple of 4 KB. The spare 1 KB is reserved inside the slot, never given to a neighbour.

Expect to sketch a map on a whiteboard with sizes, bases, one alias and one hole, then defend every choice. The four lessons are that defence in order.

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See also

  • Implementing Address Decode
  • Decode Errors and Default Slaves
  • Register Maps and Banks