The address map is the first document an integrator writes and the last one anyone is allowed to change casually. This topic builds it from scratch on NanoSoC: what a region promises, why every window is a power of two sitting on a multiple of its own size, what lives in the holes between regions, why the DMA appears sixteen times, and how to leave room for the next peripheral without moving anything. Every number comes from the NanoSoC design specification.
Lesson | After it you can... |
|---|---|
Read the NanoSoC map as a contract and name every region attribute. | |
Justify each base and size, and run the alignment and overlap checker. | |
Say what answers in each hole and why software must never probe one. | |
Place a second DMA and a bigger SRAM without moving any existing region. |
Suggested order: top to bottom. The first lesson reads the map, the second checks its arithmetic, the third walks the empty spaces, and the fourth grows it. The decode topic next door (Implementing Address Decode) turns this map into gates.
4 KB: windows are powers of two, so 3 KB rounds up to 4 KB, and the base must be a multiple of 4 KB. The spare 1 KB is reserved inside the slot, never given to a neighbour.