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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
    • Designing the Address Map
    • Implementing Address Decode
    • Decode Errors and Default Slaves
    • Register Maps and Banks
    • Security and Privilege Regions
    • The Software View and the Hardware-Software Contract
    • IP-XACT and Automated Assembly
      • What IP-XACT Describes
      • Generating the Top from One Description
      • Reviewing Generated Output
    • Memory-Map Verification
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Memory Maps and Address Decode
  1. Topics
  2. SoC Design
  3. Memory Maps and Address Decode
  4. IP-XACT and Automated Assembly

Part 3 of 14Part 3 of 14/Memory Maps and Address DecodeAll levels

IP-XACT and Automated Assembly

One machine-readable chip description generating the wiring, decode, headers and documents, and where that automation fails.

  • 3topics
  • 3lessons

Assembling a chip top by hand means typing the same facts many times: once in the wiring, once in the decode, once in the headers, once in the documents. Automated assembly types each fact once, in a standard description, and generates the rest. IP-XACT (IEEE 1685) is the public standard format for that description; this topic explains what it carries at a conceptual level, generates NanoSoC's wiring and decode from a small description written as data, and then reviews honestly where the automation stops helping. The emphasis is on judgement: what to generate, what to review, and what never to trust a generator with unattended.

Lesson

After it you can...

What IP-XACT Describes

Name what a component and a design description carry, and what they do not.

Generating the Top from One Description

Generate wiring, decode and headers from a small NanoSoC description and assert completeness.

Reviewing Generated Output

Review generator output with a checklist and name its characteristic failure modes.

Suggested order: top to bottom. The vocabulary first, then a working miniature generator, then the scepticism that keeps generated silicon honest. No vendor tools are named anywhere in this topic, deliberately: the ideas outlive any particular implementation of the flow.

Check yourself Why generate the top level at all instead of writing it once, carefully?

Because it is not written once. Every block delivery, parameter change and map change reopens it, and each manual reopening is a chance for the copies to disagree. Generation makes disagreement a build error instead of a silicon bug.

Expect to describe a single-source flow: what is described, what is generated, what is checked, and where you stop trusting it. Lesson three is the part most candidates skip.

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See also

  • Designing the Address Map
  • Implementing Address Decode
  • Decode Errors and Default Slaves