Inside every 4 KB slot lives a register block, and its table is a second, smaller contract stacked on the address map: which offset, how wide, who may write it, and what it holds after reset. NanoSoC carries seven of these tables, from the DMA's five registers to the reset controller's eight, and they already contain the three register bugs every integrator meets: a control write that silently clears an interrupt enable, status bits that ignore writes for the wrong reason, and writes that vanish while the block is busy. This topic designs the block properly, checks the specification with a script, and builds a small working register file in SystemVerilog. For the block-level view see CSR Contract and Address Map and The Firmware Side: a C Driver.
Lesson | After it you can... |
|---|---|
Lay out offsets, widths, access types and reset values for any NanoSoC block. | |
Run a checker over a register table and catch a bad row before RTL exists. | |
Build a DMA-style register block and name its three classic failure modes. |
Suggested order: top to bottom. Design first, because the checker only enforces what the design rules state; then check the table; then watch the same rules become gates. The verification topic at the end of this section tests these blocks from software.
Because the access types are defined per bit field, not per register. BUSY ignores writes, DONE and ERR clear on a written one and ignore a written zero, so software can clear status without disturbing the busy indication.